CXA2647N
• VC Buffer
• DVC Buffer
This outputs the VC ((1/2) VCC) voltage.
This outputs the DVC ((1/2) DVCC) voltage.
The maximum output current is approximately ±3mA.
Use this voltage as the analog block VC voltage.
The maximum output current is approximately ±3mA.
Use this voltage as the digital block VC voltage.
The each output DC voltage of FE, TE and CE is
level shifted using the DVC voltage as the reference.
VCC
40k
DVCC
VC
27
25
40k
40k
14
DVC
25
40k
• RFDC
The signals input to the A, B, C and D pins are added, amplified and the RFDC signal is output. ROM/RW
switching, low frequency gain adjustment and output DC voltage adjustment are possible.
VC
Control bias
VC – 1V to VC + 1V
30
ROM
24k
RW
96k
5.1k
A
B
6
7
15k
15k
10k
RFDCI 29
28 RFDC
124
ROM
RW
124
2k
C
D
8
9
15k
15k
40k
ROM
RW
2.4k
3.3k
VC
VC
RFDC = Gain (A + B + C + D)
Low frequency gain ROM: 16.5dB
RW: 28.5dB
Cut-off frequency fc (typ.)
ROM : 15MHz
RW : 6MHz
The gain can be adjusted by the external resistance connected between Pins 28 and 29.
The output voltage offset can be adjusted by controlling the Pin 30 voltage.
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SONY [ SONY CORPORATION ]
