CXA2542AQ
Focus Servo
6k
0.022µ
FZC
FEO
54k
47
48
1
FZC
SENS
SELECTOR
SENS1
23
FE
10k
300k
FEI
100k
10k
DFCT
FS3
FS4
2200p
68k
FOCUS COIL
FE_O
FE_M
Focus
phase
Compensation
100k
2
3
5
FDFCT
FGD
0.1µ
100k
50k
6
680k
0.1µ
40k
11µ 22µ
60k
ISET
16
50k
FS1
FS2
Charge
up
FLB
FSET
10
SRCH
4.7µ
4
7
0.015µ
0.1µ
510k
The above figure shows a block diagram of the focus servo.
Ordinarily the FE signal is input to the focus phase compensation circuit through a 68kΩ resistance; however,
when DFCT is detected, the FE signal is switched to pass through a low-pass filter formed by the internal
100kΩ resistance and the capacitance connected to Pin 2. When this DFCT prevention circuit is not used,
leave Pin 2 open. The defect switch operation can be enabled and disabled with command.
The capacitor connected between Pin 4 and GND is a time constant to boost the low frequency in the normal
playback state.
The peak frequency of the focus phase compensation is approximately 1.2kHz when a resistance of 510kΩ is
connected to Pin 10.
The focus search level is approximately ±1.1Vp-p when using the constants indicated in the above figure. This
level is inversely proportional to the resistance connected between Pin 16 and VEE. However, changing this
resistance also changes the level of the track jump and sled kick as well.
The FZC comparator inverted input is set to 10% of Vcc and VC (Pin 46); (Vcc – VC) × 10%.
510kΩ resistance is recommended for Pin 10.
– 23 –
SONY [ SONY CORPORATION ]
