CXA2542AQ
• Balance adjustment
The balance adjustment is performed by passing the tracking error signal (TEO signal) through the external
LPF, extracting the offset DC, and comparing it to the reference level.
However, the TEO signal frequency distribution ranges form DC to 2kHz. Merely sending the signal through
the LPF leaves lower frequency components, and the complete offset DC can not be extracted.
To extract it, monitor the TEO signal frequency at all times, and perform adjustment only when a frequency
that can lower a sufficient gain appears on the LPF.
Use the C.OUT output to check this frequency.
The offset DC and reference level are compared by the window comparator.
The comparison signal is output from the SENS1 and SENS2 pins. (ADDRESS D11001100D6)
Adjust the balance so that the SENS1 and SENS2 pins are both High.
VIN < VL < VH
H
VL < VIN < VH
H
VL < VH < VIN
L
SENS1 pin
SENS2 pin
BALH
BALL
L
H
H
VH: High level threshold value
VIN: Window comparator input signal
VL: Low level threshold value
• Gain adjustment
Gain adjustment is performed by passing the TEO signal through the HPF and comparing the AC component
to the reference level.
The AC component is generated by taking the difference between TE and the offset DC input to Pin 42.
The AC component and reference level are compared by the window comparator.
The comparison signal is output from the SENS1 and SENS2 pins. (ADDRESS D11001101D6)
The comparison signal is as follows.
(1)
(2)
(3)
VH
VL
VIN
H
H
SENS1 pin
TGH
SENS2 pin
TGL
L
The gain should be adjusted so that the SENS1 and SENS2 pins are as shown in status (2).
When the TEO signal level is low and TGH (SENS1 pin) does not go Low, the gain should be raised with the
TGFL command for adjustment. If the adjustment does not bring the result of Low, check the pulse duty of TGL
(SENS2 pin).
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SONY [ SONY CORPORATION ]
