CXA2095S
5) C signal processing
The chroma signal input to Pin 5 (specified input level: level at which a 40 IRE burst level signal with a gain of
6dB with respect to the video signal standard becomes a 570mVp-p signal) passes through the ACC, TOT
(secondary HPF), color control and demodulation circuits. The signal then becomes the R-Y and B-Y color
difference signal and is input to the YUV SW circuit. When the burst level goes to –31dB or less with respect to
the specified input level, the color killer operates and the color difference signal is not output.
The external Y, color difference signals input to Pins 10, 11 and 12 pass through the clamp and amplifier
circuits and are input to the YUV SW circuit. The YUV SW circuit is controlled by the YUV SW (Pin 9).
However, its operation differs depending on the data in the I2C bus register (EY-SW). In other words, the YUV
SW circuit output is as follows.
When EY-SW = 0: Internal Y/color difference signal when YUV SW is low,
external Y/color difference signal (Pins 9, 10 and 11) when YUV SW is high
When EY-SW = 1: Internal Y/color difference signal when YUV SW is low,
internal Y/external color difference signal when YUV SW is high
When external Y/color difference signal is selected , the picture quality can be adjusted in the same manner as
with the normal internal Y signal by setting EY-SW to 1 and then inputting the external Y signal to YIN (Pin 4).
However, in this case the delay time between the Y signal and color difference signals must be realigned.
The specified input level for the external Y signal is the level at which a normal video signal standard, 100 IRE,
100% white signal becomes a 0.7Vp-p signal. The specified input level for the external color difference signal
is the level at which a normal video signal standard, 40 IRE burst level demodulates a 258mVp-p chroma
signal at orthogonal coordinates to become a 0.8 times signal (R-Y is demodulated by the 90° axis to become
a 1.14 times signal, B-Y is demodulated by the 0° axis to become a 2.03 times signal).
The G-Y signal is generated as the base of Y, color difference signals at the axis adjustment circuit. The Y
signal is added to R-Y, G-Y, and B-Y respectively and these signals become R, G, and B signals. And they are
input to the RGB block.
6) RGB signal processing
The RGB signals obtained from the Y/C block pass through the half-tone switch circuit (YM SW), the switch
circuit for the external RGB signal (YS SW), the picture control, dynamic color, gamma compensation, clamp,
brightness control, drive adjustment, cut-off adjustment and auto cut-off circuits, and are output to Pins 20, 22
and 24.
The RGB signals input to Pins 16, 17 and 18 are the level at which a normal video signal standard, 100 IRE,
100% white signal becomes a 0.7Vp-p signal.
The voltage applied to Pin 26 (ABLIN) is compared with the internal reference voltage, integrated by the
capacitor which is connected to Pin 27, and performs picture control and brightness control. In order to adjust
the white balance (black balance), this IC has a drive control function which adjusts the gain between the RGB
outputs and a cut-off control function which adjusts the DC level between the RGB outputs. Both drive control
and cut-off control are adjusted by the I2C bus, with the Rch fixed and the G and Bch variable. An auto cut-off
function (AKB) which forms a loop between the IC and CRT and performs adjustment automatically has also
been added. This function can compensate for changes in the CRT with time. Auto cut-off operation is as
follows.
• R, G and B reference pulses for auto cut-off, shifted 1H each in the order mentioned, appear at the top of
the picture (actually, in the overscan portion). The reference pulse uses 1H in the V blanking interval, and is
output from each R, G and B output pin.
• The cathode current (IK) of each R, G and B output is converted to a voltage and input to Pin 25.
• The voltage input to Pin 25 is compared with the reference voltage in the IC, and the current generated by
the resulting error voltage charges the capacitors connected to Pins 19, 21 and 23 for the reference pulse
interval and is held during all other interval.
• The loop functions to change the DC level of the R, G and B outputs in accordance with the capacitor pin
voltage so that the Pin 25 voltage matches the reference voltage in the IC.
The Rch for the reference voltage in the IC is fixed and the G and Bch are cut-off controlled by the I2C bus.
During G/B-CUTOFF center status, the loop functions so that the Rch, Gch and Bch for the reference pulse
input to Pin 25 is all 1Vp-p.
The reference pulse timing can be varied by the I2C bus.
When AKB is not used, the IC can be set to manual cut-off adjustment mode with I2C bus settings. In this
case, the DC level of the R, G and B outputs can be varied by applying voltages independently to Pins 19, 21
and 23.
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SONY [ SONY CORPORATION ]
