CXA2095S
3. Signal processing
The CXA2095S is comprised of sync signal processing, H deflection signal processing, V deflection signal
processing, and Y/C/RGB signal processing blocks, all of which are controlled by the I2C bus.
1) Sync signal processing
The Y signals input to Pins 43 and 44 are sync separated by the horizontal and vertical sync separation
circuits. The resulting horizontal sync signal and the signal obtained by frequency dividing the 32 FH-VCO
output using the ceramic oscillator (frequency 503.5kHz) by 32 are phase-compared, the AFC loop is
constructed, and an H pulse synchronized with the H sync is generated inside the IC. Adjustment of the H
oscillator frequency is unnecessary. When the AFC is locked to the H sync, 1 is output to the status register
(HLOCK) and that can be used to detect the presence of the video signal.
The vertical sync signal is sent to the V countdown block where the most appropriate window processing is
performed to obtain V sync timing information which resets the counter. AKB and other V cycle timing are then
generated from this reset timing.
2) H deflection signal processing
The H pulse obtained through sync processing is phase-compared with the H deflection pulse input from Pin
36 to control the phase of the HDRIVE output, and so the horizontal position of the image projected on the
CRT is controled. In addition, the compensation signal generated from the V sawtooth wave is superimposed.
As a result, the vertical picture distortion is compensated.
The H deflection pulse is used to H blank the video signal. When the pulse input from Pin 36 has a narrow
width, the pulse generated by the IC can be added to the H deflection pulse and used as the H blanking pulse.
(HBLKSW)
Pin 36 is normally pulse input, but if the pin voltage drops to the GND level, HDRIVE output goes to high level
(DC) and 1 is output to the status register (HNG). To release this status, turn the power off and then on again.
3) V deflection signal processing
The V sawtooth wave is generated at the cycle of the reset pulse output from the countdown system. After
performing wide deflection processing for this sawtooth wave, picture distortion adjustment is performed by the
VDRIVE and E/WDRIVE function circuits and the signal is output as the VDRIVE and E/WDRIVE signals.
4) Y signal processing
The Y signal input to Pin 4 (specified input level: level at which a 100% white (including sync, 140 IRE) signal
with a gain of 6dB with respect to the video signal standard becomes a 2Vp-p signal) passes through the
subcontrast control, trap for eliminating the chroma signal, sharpness control, clamp and black expansion
circuits, and is then input to the switching circuit (YUV SW) for the external Y/color difference signal. The
differential waveform of the Y signal delayed for approximately 200ns from the Y input is output from Pin 45 as
the signal for VM.
The VM signal is not output in the following cases.
When EY-SW = 0 and YUV SW (Pin 9) or YS (Pin 15) is high
When EY-SW = 1 and YS (Pin 15) is high
The f0 of the built-in filter is automatically adjusted inside the IC, but the trap f0 may require fine adjustment by
the I2C bus (CTRAP-ADJ) if it is affected by variation. When inputting a signal which has been Y/C separated
by a comb filter, etc., the trap should be turned OFF.
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SONY [ SONY CORPORATION ]
