CXA2095S
Description of Operation
1. Power-on sequence
The CXA2095S does not have an internal power-on sequence. Therefore, all IC operations are controlled by
the set microcomputer (I2C bus controller).
1) Power-on
The IC is reset and the RGB outputs are all blanked. Hdrive starts to oscillate, but oscillation is at the
maximum frequency (16kHz or more) and is not synchronized to the input signal. Output of vertical signal
VTIM starts, VDRIVE outputs V sawtooth wave. Bus registers which are set by power-on reset are as follows.
AGING1
AGING2
RON
= 0: All white output aging mode OFF
= 0: All black output aging mode OFF
= 0: Rch video blanking ON
GON
= 0: Gch video blanking ON
BON
= 0: Bch video blanking ON
PICON
VOFF
FHHI
= 0: RGB all blanking ON
= 0: V sawtooth wave oscillation mode
VOFF = 1 for the CXA2025S.
= 1: H oscillator maximum frequency mode
CD-MODE = 0: Automatic selector mode of the countdown mode
AKBOFF = 0: AKB mode
2) Bus register data transfer
The register setting sequence differs according to the set sequence. Register settings for the following
sequence are shown as an example.
Set sequence
Power-on
↓
CXA2095S register settings
Reset status in 1) above.
↓
Degauss
Reset status in 1) above.
The CRT is degaussed in the completely darkened condition.
↓
↓
IC initial setting
The IC is set to the power-on initial settings. (See the following page.)
The HDRIVE oscillator frequency goes to the standard frequency (around
15.734kHz).
↓
↓
AKB operation start
PICON is set to 1 and a reference pulse is output from Rout, Gout and
Bout. Then, the IC waits for the cathode to warm up and the beam current
to start flowing.
↓
↓
AKB loop stable
Status register IKR is monitored.
IKR = 0: No cathode current
IKR = 1: Cathode current
Note that the time until IKR returns to 1 differs according to the initial
status of the cathode.
↓
↓
Video output
RON, GON and BON are set to 1 and the video signal is output from
Rout, Gout and Bout.
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SONY [ SONY CORPORATION ]
