CXA2094Q
Mode Control Table 3
TVOUT-R
MUTE
M1
TVSW
EXT
—
—
0
FEXT1
FEXT2
TVOUT-L
MUTE
1
2
3
4
5
6
0
1
1
1
1
1
—
0
—
—
0
—
—
—
—
0
TV (R)
TV (L)
AUX1-R
AUX1-L
AUX2-R
AUX2-L
1
AUX1-L
AUX1-L
AUX2-L
AUX2-L
1
0
1
1
1
—
—
1
1
1
TV (L) / TV (R) are selected in MATRIX
TV (L): MONO, ST-L, SAP, (SAPBPFout, D/Aout)
TV (R): MONO, ST-R, SAP, (NRBPFout, STVCO freerun (4fH))
I2C BUS block items (SDA, SCL)
No.
1
Item
Symbol
VIH
VIL
Min. Typ.
Max.
5.0
1.5
10
10
0.4
—
Unit
V
High level input voltage
Low level input voltage
High level input current
Low level input current
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3.0
0
2
3
IIH
—
—
0
µA
4
IIL
Low level output voltage SDA (Pin 48) during 3mA inflow
Maximum inflow current
V
5
VOL
IOL
mA
pF
6
3
Input capacitance
10
100
—
7
CI
—
0
Maximum clock frequency
kHz
8
fSCL
tBUF
Minimum waiting time for data change
Minimum waiting time for start of data transfer
Low level clock pulse width
9
4.7
—
10
11
12
13
14
15
16
17
18
tHD: STA 4.0
—
tLOW
tHIGH
4.7
4.0
µs
High level clock pulse width
Minimum waiting time for start preparation
Minimum data hold time
—
—
tSU: STA 4.7
tHD: DAT
tSU: DAT 250
—
0
Minimum data preparation time
Rise time
—
ns
µs
ns
µs
1
tR
tF
—
—
Fall time
300
—
Minimum waiting time for stop preparation
tSU: STO 4.7
I2C BUS load conditions: Pull-up resistor 4kΩ (Connect to +5V)
Load capacity 200pF (Connect to GND)
– 26 –
SONY [ SONY CORPORATION ]
