CXA2069Q
A-IN1 to A-IN2 (3 each) : These bits select the input signals output to each audio output.
A-IN1 corresponds to the LOUT1/ROUT1 outputs, and A-IN2 to the LOUT2/ROUT2 outputs.
0 : Mute
4 : Selects the LV3/RV3 inputs
5 : Selects the LV4/RV4 inputs
6 : Selects the LV5/RV5 inputs
7 : Selects the LV6/RV6 inputs
1 : Selects the LTV/RTV inputs
2 : Selects the LV1/RV1 inputs
3 : Selects the LV2/RV2 inputs
AV-IN3 (3) : This bit selects the input signals output to output 3.
Both the video output and the audio output are selected at the same time only for AV-IN3.
0 : Mute
4 : Selects the V3, Y3/C3 and LV3/RV3 inputs
5 : Selects the V4, Y4/C4 and LV4/RV4 inputs
1 : Selects the TV and LTV/RTV inputs
2 : Selects the V1, Y1/C1 and LV1/RV1 inputs 6 : Selects the V5 and LV5/RV5 inputs
3 : Selects the V2, Y2/C2 and LV2/RV2 inputs 7 : Selects the V6 and LV6/RV6 inputs
DC OUT (2) : These bits set the DC voltage output from Pin 35 (DC OUT).
0 : 4.5 V
1 : 0 V
2 : 1.9 V
3 : 4.5 V
3) Status Registers
• When reading two bytes
S
Slave address
• When reading one byte
Slave address
A
DATA1
DATA1
A
DATA2
NA P
S
A
NA P
S ; Start condition
A ; Acknowledge
NA ; No acknowledge
P ; Stop condition
When communication is to be terminated in the status register reading mode, the “no-acknowledge”
signal is needed to assure that the master does not issue the acknowledge signal to the slave.
It is possible to read only DATA1 of the status register by sending the no-acknowledge signal after
DATA1.
O Status register structure (DATA1 to DATA2)
b7
b6
b5
b4
b3
0
b2
0
b1
b0
1
Slave add.
DATA1
1
0
0
1
ADR
S1SEL
S1SEL
S2SEL
S2SEL
S3SEL
S3SEL
S4SEL
S4SEL
S-C1
S-C3
S-C2
S-C4
DATA2
—16—
SONY [ SONY CORPORATION ]
