CXA2069Q
2) Control Registers
The CXA2069Q control is exercised by writing 3-byte data into the three 8-bit control registers which
control the output selector circuits for the 3 outputs.
S
Slave address
A
DATA1
A
DATA2
A
DATA3
A
P
S ; Start condition
A ; Acknowledge
P ; Stop condition
O Control register structure (DATA1 to DATA3)
• All registers are set to “0” during IC power on.
• “ ” indicates undefined.
b7
1
b6
0
b5
0
b4
b3
b2
b1
b0
Slave add.
DATA1
1
0
0
ADR
A-IN1
R/W
A-GAIN S/COMP1
V/YOUT S/COMP2
S/COMP3
V-IN1
V-IN2
AV-IN3
DATA2
A-IN2
DATA3
DC OUT
R/W (1) : Read/write mode
0 : Control data write
1 : Status register read
ADR (1) : This bit sets the slave address set by the address pin.
0 : 90H
1 : 92H
A-GAIN (1) : LOUT1/ROUT1 output gain selector
0 : 0 dB output
1 : –6 dB output
S/COMP1 to S/COMP3 (1 each) : S terminal input/composite signal input selectors
By setting S/COMP1 to “0”, when composite signal input is selected, YOUT1/COUT1 output the
inputs from YIN1/CIN1 during video 1 output.
0 : Composite signal inputs (TV, V1 to V6 inputs)
1 : S terminal inputs (Y1/C1 to Y4/C4 inputs)
V/YOUT (1) : This bit selects the output to Pin 44 (V/YOUT2).
0 : VOUT (composite signal) output
1 : YOUT (luminance signal) output
V-IN1 to V-IN2 (3 each) : These bits select the input signals output to each video output.
V-IN1 corresponds to the VOUT1 and YOUT1/COUT1 outputs, and V-IN2 to the VOUT2 and
YOUT2/COUT2 outputs.
0 : Mute
4 : Selects the V3 and Y3/C3 inputs
5 : Selects the V4 and Y4/C4 inputs
6 : Selects the V5 input
1 : Selects the TV input
2 : Selects the V1 and Y1/C1 inputs
3 : Selects the V2 and Y2/C2 inputs
7 : Selects the V6 input
—15—
SONY [ SONY CORPORATION ]
