CXA2067AS
I2C Bus Logic System
No.
Item
Symbol
VIH
Min.
3.0
0
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
5.0
1.5
0.4
400
—
Unit
V
1
2
3
4
5
6
7
8
9
High level input voltage
Low level input voltage
VIL
V
Low level output voltage with 3 mA
SDA current inflow
VOL
0
V
Maximum clock frequency
fSCL
0
kHz
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
Minimum waiting time for data change
tBUF
4.0
4.0
4.7
4.0
4.7
0
Minimum waiting time for data
transmission start
tHD : STA
tLOW
—
Low level clock pulse width
High level clock pulse width
—
tHIGH
—
Minimum waiting time for start
preparation
tSU : STA
tHD : DAT
tSU : DAT
tR
—
10 Minimum data hold time
11 Minimum data preparation time
12 Rise time
—
250
—
—
1
13 Fall time
tF
—
300
—
Minimum waiting time for stop
14
tSU : STO
4.7
preparation
—9—
SONY [ SONY CORPORATION ]
