CXA2067AS
Sub Address VDET LEVEL (2): Controls the signal detection (VDET) slice level.
0101
0 : Slice level minimum (RIN or GIN or BIN=30 mV)
1 : Slice level maximum (RIN or GIN or BIN=220 mV)
Sub Address OSD GAIN (6):
0110
Performs the OSD gain control for R, G and B channels in common.
Control is performed by the multiplication with SUB CONTRAST (upper 6
bits) so that the video white balance and tracking are obtained.
0 : Gain minimum (0 Vp-p)
63 : Gain maximum (5 Vp-p)
Sub Address CUT OFF RGB (8): Performs the Pin 6 (COF RGB) output voltage.
0110
0 : Output voltage minimum (1 V)
255 : Output voltage maximum (4 V)
Sub Address SUB CONTRAST R (8): Performs the R channel gain control.
0111 Control is performed by the multiplication with CONTRAST. Use for
the white balance adjustment.
0 : Gain minimum (–30 dB or less)
255 : Gain maximum (+17 dB)
Sub Address SUB CONTRAST G (8): Performs the G channel gain control.
1000 Control is performed by the multiplication with CONTRAST. Use for
the white balance adjustment.
0 : Gain minimum (–30 dB or less)
255 : Gain maximum (+17 dB)
Sub Address SUB CONTRAST B (8): Performs the B channel gain control.
1001
Control is performed by the multiplication with CONTRAST. Use for
the white balance adjustment.
0 : Gain minimum (–30 dB or less)
255 : Gain maximum (+17 dB)
Sub Address VDET OFF (1):
1010
Performs the Pin 30 output control.
0 : Output ON
1 : Output OFF
Sub Address SV SW (1):
1010
Switches the Pin 30 output signal (sync separator/video detector).
0 : Sync separator output
1 : Video detector output
Sub Address VS OFF (1):
1010
Performs the control of VBLK sync DAC refresh function.
0 : Function operation ON
1 : Function operation OFF
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SONY [ SONY CORPORATION ]
