ACX306AK
Clock Timing Conditions of Panel Block
(VIH = 3.0V, VDD = 12V, Ta = 25°C)
Item
Symbol
trHst
Min.
—
Typ.
—
Max.
30
Unit
HST rise time
HST fall time
HST
tfHst
—
—
30
HST data setup time
HST data hold time
HCKn 5 rise time
tdHst
300
–30
—
333
0
363
30
thHst
trHckn
tfHckn
to1Hck
to2Hck
trVst
—
30
ns
HCKn 5 fall time
HCK
—
—
30
HCK1 fall to HCK2 rise time
HCK1 rise to HCK2 fall time
VST rise time
–15
–15
—
0
15
0
15
—
100
100
34
VST fall time
VST
tfVst
—
—
VST data setup time
tdVst
30
32
–32
—
µs
ns
µs
VST data hold time
thVst
–30
—
–34
100
100
100
100
700
3100
100
100
–0.6
1.6
VCK rise time
VCK
trVckn
tfVckn
trEn
VCK fall time
—
—
EN rise time
—
—
EN fall time
EN
tfEn
—
—
EN fall to VCK rise/fall time
tdEn
500
2900
—
600
3000
—
EN pulse width
twEn
WIDE rise time
trWide
tfWide
tdhWide
twhWide
WIDE fall time
WIDE
—
—
WIDE (H) rise to VCK rise/fall time
–0.4
1.4
–0.5
1.5
WIDE (H) pulse width
5
HCKn means HCK1 and HCK2. (fHCKn = 1.5MHz)
– 7 –
SONY [ SONY CORPORATION ]
