ACX306AK
2. Panel input signal voltage conditions
(VSS = 0V)
Item
Symbol
VIL
Min.
–0.3
Typ.
0.0
Max.
0.3
Unit
V
(Low)
(High)
H/V driver input voltage
VIH
2.6
3.0
5.5
V
REF input voltage
VREF
VVC
VIH/2 – 0.3
5.8
VIH/2
6.0
VIH/2 + 0.3
6.2
V
4
Video signal center voltage
V
VDDG – 4.0
(10.5V or less)
4
Video signal input range
Vsig
1.0
VVC ± 4.0
V
4
Uniformity improvement signal
Vpsig
VVC ± 2.3 VVC ± 2.5
VVC – 0.6 VVC – 0.5
VVC ± 2.7
VVC – 0.4
V
V
Common voltage of panel (Ta = 25°C) Vcom
4
Input video and uniformity improvement signals should be input the voltage amplitude symmetrical to VVC
as shown in Fig. 1.
PSIG waveform
Vpsig
VVC
Fig. 1
Pin Description of Panel Block
Pin
No.
Pin
No.
Symbol
TESTL
COM
VST
Description
Symbol
HST
Description
Start pulse input for H shift register
drive
1
2
13
14
15
16
17
18
19
20
21
22
23
24
Panel test output; no connection
Common voltage input of panel
Level shifter circuit REF voltage
input
REF
Start pulse input for V shift register
drive
3
TEST
Panel test output; no connection
Cext/
Rext
Time constant power supply input
for H shift register drive
4
VCK
Clock input for V shift register drive
Gate selection pulse enable input
5
EN
HCK2
HCK1
PSIG
Clock input for H shift register drive
Clock input for H shift register drive
Uniformity improvement signal input
V shift register drive direction signal
input
6
DWN
VDD
7
Power supply input for V driver
H and V driver GND
8
VSS
GREEN Video signal (G) input to panel
Boost power supply setting for
V driver
9
VDDG
VSSG
TEST2
WIDE
RED
BLUE
RGT
Video signal (R) input to panel
Video signal (B) input to panel
Negative power supply setting for
V driver
10
11
12
H shift register drive direction signal
input
No connection inside the panel.
(with 1MΩ terminating resistor)
Uniformity improvement signal
control pulse input
TESTR Panel test output; no connection
– 4 –
SONY [ SONY CORPORATION ]
