ACX306AK
2. Description of LCD Panel Operations
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to each of 240 line electrodes sequentially one line electrode at a time in a single horizontal scanning period.
• The selected pulse is output when the enable pin goes to high level. PAL signal pulse elimination display is
possible by using the enable pin and simultaneously controlling VCK.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuitry,
applies selected pulses to each of 490 signal electrodes sequentially in a single horizontal scanning period.
These pulses are used to supply the sampled video signal to the row signal lines.
• The scanning direction of the horizontal shift registers can be switched with the RGT pin. The scanning
direction is left to right (right scan) for RGT pin at high level (2.6 to 5.5V), and right to left (left scan) for RGT
pin at low level (0V). In addition, the scanning direction of the vertical shift registers can be switched with the
DWN pin. The scanning direction is top to bottom for DWN pin at high level (2.6 to 5.5V), and bottom to top
for DWN pin at low level (0V). (These scanning directions are from a front view.)
• The vertical and horizontal drivers address one pixel, and then thin film transistors (TFTs; two TFTs for one
pixel) turn on to apply a video signal to the pixel. The same procedures lead to the entire 240 × 490 pixels to
display a picture in a single vertical scanning period.
• Pixel dots are arranged in a delta pattern, where sets of RGB pixels are positioned shifted by 1.5 dots against
adjacent horizontal lines. The horizontal driver output pulse must be shifted by 1.5 dots for each horizontal
line against the horizontal sync signal to apply a video signal to each pixel properly.
• The video signal should be input with the polarity-inverted every horizontal cycle.
• The relationships between the vertical shift register start pulse VST and the vertical display period, and
between the horizontal shift register start pulse HST and the horizontal display period are shown below for
top to bottom and left to right scan.
(1) Vertical display period (DWN: high level)
VD
VST
VCK
2
240
1
239
Vertical display period 240H (14.5ms)
(2) Vertical display period (DWN: low level)
VD
VST
1
2
239
240
VCK
Vertical display period 240H (14.5ms)
(3) Horizontal display period (RGT: high level)
BLK
HST
165
164 166
HCK1
HCK2
1
2
3
Horizontal display period (54.6µs)
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SONY [ SONY CORPORATION ]
