SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
6.2 INTEN INTERRUPT ENABLE REGISTER
INTEN is the interrupt request control register including four internal interrupts, three external interrupts enable control
bits. One of the register to be set “1” is to enable the interrupt request function. Once of the interrupt occur, the stack is
incremented and program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service
routine when the returning interrupt service routine instruction (RETI) is executed.
0C9H
INTEN
Read/Write
After reset
Bit 7
ADCIEN
R/W
Bit 6
Bit 5
TC0IEN
R/W
Bit 4
T0IEN
R/W
0
Bit 3
CM2IEN
R/W
Bit 2
CM1IEN
R/W
Bit 1
CM0IEN
R/W
Bit 0
P00IEN
R/W
-
-
-
0
0
0
0
0
0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 7
P00IEN: External P0.0 interrupt (INT0) control bit.
0 = Disable INT0 interrupt function.
1 = Enable INT0 interrupt function.
CM0IEN: Comparator 0 interrupt control bit.
0 = Disable comparator 0 interrupt function.
1 = Enable comparator 0 interrupt function.
CM1IEN: Comparator 1 interrupt control bit.
0 = Disable comparator 1 interrupt function.
1 = Enable comparator 1 interrupt function.
CM2IEN: Comparator 2 interrupt control bit.
0 = Disable comparator 2 interrupt function.
1 = Enable comparator 2 interrupt function.
T0IEN: T0 timer interrupt control bit.
0 = Disable T0 interrupt function.
1 = Enable T0 interrupt function.
TC0IEN: TC0 timer interrupt control bit.
0 = Disable TC0 interrupt function.
1 = Enable TC0 interrupt function.
ADCIEN: ADC interrupt control bit.
0 = Disable ADC interrupt function.
1 = Enable ADC interrupt function.
SONiX TECHNOLOGY CO., LTD
Page 58
Version 2.0
SONIX [ SONIX TECHNOLOGY COMPANY ]
