SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
13.3 ADC DATA BUFFER REGISTERS
ADC data buffer is 12-bit length to store ADC converter result. The high byte is ADB register, and the low-nibble is
ADR[3:0] bits. The ADB register is only 8-bit register including bit 4~bit11 ADC data. To combine ADB register and the
low-nibble of ADR will get full 12-bit ADC data buffer. The ADC data buffer is a read-only register and the initial status
is unknown after system reset.
ADB[11:4]: In 8-bit ADC mode, the ADC data is stored in ADB register.
ADB[11:0]: In 12-bit ADC mode, the ADC data is stored in ADB and ADR registers.
0B2H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADB
ADB11
ADB10
ADB9
ADB8
ADB7
ADB6
ADB5
ADB4
Read/Write
After reset
R
-
R
-
R
-
R
-
R
-
R
-
R
-
R
-
Bit[7:0]
ADB[7:0]: 8-bit ADC data buffer and the high-byte data buffer of 12-bit ADC.
0B3H
ADR
Read/Write
After reset
Bit 7
Bit 6
ADCKS1
R/W
Bit 5
ADLEN
R/W
Bit 4
ADCKS0
R/W
Bit 3
ADB3
R
-
Bit 2
ADB2
R
-
Bit 1
ADB1
R
-
Bit 0
ADB0
R
-
-
-
-
0
0
0
Bit [3:0] ADB [3:0]: 12-bit low-nibble ADC data buffer.
The AIN input voltage v.s. ADB output data
AIN n
ADB11 ADB10
ADB9
ADB8
ADB7
ADB6
ADB5
ADB4
ADB3
ADB2
ADB1
ADB0
0/4096*VREFH
1/4096*VREFH
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
4094/4096*VREFH
4095/4096*VREFH
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
For different applications, users maybe need more than 8-bit resolution but less than 12-bit. To process the ADB and
ADR data can make the job well. First, the ADC resolution must be set 12-bit mode and then to execute ADC converter
routine. Then delete the LSB of ADC data and get the new resolution result. The table is as following.
ADB
ADB8
ADR
ADC Resolution
ADB11
ADB10 ADB9
ADB7
O
O
O
O
ADB6
O
O
O
O
ADB5
O
O
O
O
ADB4
O
O
O
O
ADB3
x
O
O
O
O
ADB2
ADB1
ADB0
x
x
x
x
8-bit
9-bit
10-bit
11-bit
12-bit
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
x
x
O
O
O
x
x
x
O
O
O
O
O
O
O
O = Selected, x = Useless
Note: The initial status of ADC data buffer including ADB register and ADR low-nibble after the system
reset is unknown.
SONiX TECHNOLOGY CO., LTD
Page 110
Version 2.0
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