SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
13.2 ADC MODE REGISTER
ADM is ADC mode control register to configure ADC configurations including ADC start, ADC channel selection, ADC
high reference voltage source and ADC processing indicator…These configurations must be setup completely before
starting ADC converting.
0B1H
ADM
Read/Write
After reset
Bit 7
ADENB
R/W
Bit 6
ADS
R/W
0
Bit 5
EOC
R/W
0
Bit 4
GCHS
R/W
0
Bit 3
AVREFH
R/W
Bit 2
CHS2
R/W
0
Bit 1
CHS1
R/W
0
Bit 0
CHS0
R/W
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ADENB: ADC control bit. In power saving mode, disable ADC to reduce power consumption.
0 = Disable ADC function.
1 = Enable ADC function.
ADS: ADC start control bit. ADS bit is cleared after ADC processing automatically.
0 = ADC converting stops.
1 = Start to execute ADC converting.
EOC: ADC status bit.
0 = ADC progressing.
1 = End of converting and reset ADS bit.
GCHS: ADC global channel select bit.
0 = Disable AIN channel.
1 = Enable AIN channel.
AVREFH: ADC high reference voltage source control bit.
0 = Internal Vdd. P4.0 is GPIO or AIN0 pin.
1 = Enable external reference voltage from P4.0.
Bit [2:0] CHS[2:0]: ADC input channel select bit.
000 = AIN0, 001 = AIN1, 010 = AIN2, 011 = AIN3, 100 = AIN4, 101 = AIN5, 110 = AIN6, 111 = AIN7
ADR register includes ADC mode control and ADC low-nibble data buffer. ADC configurations including ADC clock rate
and ADC resolution. These configurations must be setup completely before starting ADC converting.
0B3H
ADR
Read/Write
After reset
Bit 7
Bit 6
ADCKS1
R/W
Bit 5
ADLEN
R/W
Bit 4
ADCKS0
R/W
Bit 3
ADB3
R
-
Bit 2
ADB2
R
-
Bit 1
ADB1
R
-
Bit 0
ADB0
R
-
-
-
-
0
0
0
Bit 6,4
Bit 5
ADCKS [1:0]: ADC‟s clock rate select bit.
00 = Fcpu/16, 01 = Fcpu/8, 10 = Fcpu/1, 11 = Fcpu/2
ADLEN: ADC‟s resolution select bits.
0 = 8-bit.
1 = 12-bit.
SONiX TECHNOLOGY CO., LTD
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