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SN8P2742PDB 参数 Datasheet PDF下载

SN8P2742PDB图片预览
型号: SN8P2742PDB
PDF下载: 下载PDF文件 查看货源
内容描述: [ADC, OP-amp, Comparator 8-Bit Micro-Controller]
分类和应用:
文件页数/大小: 136 页 / 3074 K
品牌: SONIX [ SONIX TECHNOLOGY COMPANY ]
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SN8P2740 Series  
ADC, OP-amp, Comparator 8-Bit Micro-Controller  
8.3.5 TC0M MODE REGISTER  
TC0M is TC0 timer mode control register to configure TC0 operating mode including TC0 pre-scalar, clock source,  
PWM function…These configurations must be setup completely before enabling TC0 timer.  
0B4H  
TC0M  
Read/Write  
After reset  
Bit 7  
TC0ENB  
R/W  
Bit 6  
TC0rate2  
R/W  
Bit 5  
TC0rate1  
R/W  
Bit 4  
TC0rate0  
R/W  
Bit 3  
TC0CKS  
R/W  
Bit 2  
TC0DIR  
R/W  
Bit 1  
TC0PO  
R/W  
Bit 0  
PWM0OUT  
R/W  
0
0
0
0
0
0
0
0
Bit 0  
PWM0OUT: PWM0 output and pulse generator output control bit.  
TC0PO = 0:  
0 = Disable PWM0 output function, and P0.1 is GPIO mode.  
1 = Enable PWM0 output function, and PWM0 signal outputs through P0.1 pin.  
TC0PO = 1:  
0 = Stop pulse output, or the end of pulse output cleared automatically.  
1 = Enable pulse output.  
Bit 1  
Bit 2  
Bit 3  
TC0PO: TC0 pulse output function control bit.  
0 = Disable.  
1 = Enable TC0 pulse output function through P0.1 pin. \  
TC0DIR: PWM0 and Pulse generator output phase select bit.  
0 = Normal phase. High pulse and low idle status.  
1 = Inverse phase. Low pulse and high idle status.  
TC0CKS: TC0 clock source select bit.  
0 = TC0 clock source is internal system clock (Fcpu).  
1 = TC0 clock source is high clock source (Fhosc).  
Bit [6:4] TC0RATE [2:0]: TC0 timer clock source select bits.  
TC0CKS = 0:  
000 = Fcpu/256, 001 = Fcpu/128, 010 = Fcpu/64, 011 = Fcpu/32, 100 = Fcpu/16, 101 = Fcpu/8, 110 =  
Fcpu/4, 111 = Fcpu/2.  
TC0CKS = 1:  
000 = Fhosc/256, 001 = Fhosc /128, 010 = Fhosc /64, 011 = Fhosc /32, 100 = Fhosc /16, 101 = Fhosc /8,  
110 = Fhosc /4, 111 = Fhosc /2.  
Bit 7  
TC0ENB: TC0 timer control bit.  
0 = Disable.  
1 = Enable.  
8.3.6 TC0C COUNTING REGISTER  
TC0C is TC0 8-bit counter. When TC0C overflow occurs, the TC0IRQ flag is set as 1and cleared by program. The  
TC0C decides TC0 interval time through below equation to calculate a correct value. It is necessary to write the correct  
value to TC0C register and TC0R register first time, and then enable TC0 timer to make sure the fist cycle correct.  
After one TC0 overflow occurs, the TC0C register is loaded a correct value from TC0R register automatically, not  
program.  
0B5H  
TC0C  
Read/Write  
After reset  
Bit 7  
TC0C7  
R/W  
0
Bit 6  
TC0C6  
R/W  
0
Bit 5  
TC0C5  
R/W  
0
Bit 4  
TC0C4  
R/W  
0
Bit 3  
TC0C3  
R/W  
0
Bit 2  
TC0C2  
R/W  
0
Bit 1  
TC0C1  
R/W  
0
Bit 0  
TC0C0  
R/W  
0
The equation of TC0C initial value is as following.  
TC0C initial value = 256 - (TC0 interrupt interval time * TC0 clock rate)  
SONiX TECHNOLOGY CO., LTD  
Page 85  
Version 2.0  
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