SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
6.10 COMPARATOR INTERRUPT OPERATION (CMP0~CMP2)
Sonix provides 3 sets comparator with interrupt function in the micro-controller. The comparator interrupt trigger edge
direction is controlled by comparator register. CM0G of CM0M is control comparator 0 interrupt trigger edge direction.
CM1G of CM1M is control comparator 1 interrupt trigger edge direction. CM2G of CM2M is control comparator 2
interrupt trigger edge direction. When the comparator output status transition occurs, the comparator interrupt request
flag will be set to “1” no matter the comparator interrupt control bit status. The comparator interrupt flag doesn‟t active
only when comparator control bit is disabled. When comparator interrupt control bit is enabled and comparator interrupt
edge trigger is occurring, the program counter will jump to the interrupt vector (ORG 8) and execute interrupt service
routine.
09CH
CM0M
Read/Write
After Reset
Bit 7
CM0EN
R/W
Bit 6
CM0OEN
R/W
Bit 5
CM0OUT
R/W
Bit 4
CM0SF
R/W
Bit 3
CM0G
R/W
0
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
0
0
0
0
Bit 3
CM0G: Comparator 0 interrupt trigger direction control bit.
0 = Falling edge trigger. Comparator output status is from high to low as CM0P < CM0N.
1 = Rising edge trigger. Comparator output status is from low to high as CM0P > CM0N.
09DH
CM1M
Read/Write
After Reset
Bit 7
CM1EN
R/W
Bit 6
CM1OEN
R/W
Bit 5
CM1OUT
R/W
Bit 4
CM1SF
R/W
Bit 3
CM1G
R/W
0
Bit 2
CM1RS2
R/W
Bit 1
CM1RS1
R/W
Bit 0
CM1RS0
R/W
0
0
0
0
0
0
0
Bit 3
CM1G: Comparator 1 output trigger direction control bit.
0 = Falling edge trigger. Comparator output status is from high to low as CM1P < CM1N.
1 = Rising edge trigger. Comparator output status is from low to high as CM1P > CM1N.
09EH
CM2M
Read/Write
After Reset
Bit 7
CM2EN
R/W
Bit 6
CM2OEN
R/W
Bit 5
CM2OUT
R/W
Bit 4
CM2SF
R/W
Bit 3
CM2G
R/W
0
Bit 2
CM2RS2
R/W
Bit 1
CM2RS1
R/W
Bit 0
CM2RS0
R/W
0
0
0
0
0
0
0
Bit 3
CM2G: Comparator 2 output trigger direction control bit.
0 = Falling edge trigger. Comparator output status is from high to low as CM2P < CM2N.
1 = Rising edge trigger. Comparator output status is from low to high as CM2P > CM2N.
Example: Setup comparator 0 interrupt request and falling edge trigger.
MOV
A, #00H
B0MOV
CM0M, A
; Set comparator 0 interrupt trigger as bi-direction edge.
B0BSET
B0BCLR
B0BSET
B0BSET
FCM0IEN
FCM0IRQ
FCM0EN
FGIE
; Enable comparator 0 interrupt service
; Clear comparator 0 interrupt request flag
; Enable comparator 0.
; Enable GIE
Example: Comparator 0 interrupt service routine.
ORG
JMP
8
; Interrupt vector
INT_SERVICE
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FCM0IRQ
EXIT_INT
; Check CM0IRQ
; CM0IRQ = 0, exit interrupt vector
B0BCLR
FCM0IRQ
; Reset CM0IRQ
…
; Comparator 0 interrupt service routine
EXIT_INT:
…
RETI
; Pop routine to load ACC and PFLAG from buffers.
; Exit interrupt vector
SONiX TECHNOLOGY CO., LTD
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Version 2.0
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