SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
6.8 TC0 INTERRUPT OPERATION
When the TC0C counter overflows, the TC0IRQ will be set to “1” no matter the TC0IEN is enable or disable. If the
TC0IEN and the trigger event TC0IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
TC0IEN = 0, the trigger event TC0IRQ is still set to be “1”. Moreover, the system won‟t execute interrupt vector even
when the TC0IEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
Example: TC0 interrupt request setup. Fcpu = 16MHz / 16.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
FTC0IEN
FTC0ENB
A, #20H
TC0M, A
A, #64H
TC0C, A
; Disable TC0 interrupt service
; Disable TC0 timer
;
; Set TC0 clock = Fcpu / 64
; Set TC0C initial value = 64H
; Set TC0 interval = 10 ms
B0MOV
B0BSET
B0BCLR
B0BSET
FTC0IEN
FTC0IRQ
FTC0ENB
; Enable TC0 interrupt service
; Clear TC0 interrupt request flag
; Enable TC0 timer
B0BSET
FGIE
; Enable GIE
Example: TC0 interrupt service routine.
ORG
JMP
8
; Interrupt vector
INT_SERVICE
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FTC0IRQ
EXIT_INT
; Check TC0IRQ
; TC0IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
…
FTC0IRQ
A, #64H
TC0C, A
; Reset TC0IRQ
; Reset TC0C.
; TC0 interrupt service routine
…
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
; Exit interrupt vector
RETI
SONiX TECHNOLOGY CO., LTD
Page 64
Version 2.0
SONIX [ SONIX TECHNOLOGY COMPANY ]
