SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
3
RESET
3.1 OVERVIEW
The system would be reset in three conditions as following.
Power on reset
Watchdog reset
Brown out reset
External reset (only supports external reset pin enable situation)
When any reset condition occurs, all system registers keep initial status, program stops and program counter is cleared.
After reset status released, the system boots up and program starts to execute from ORG 0. The NT0, NPD flags
indicate system reset status. The system can depend on NT0, NPD status and go to different paths by program.
086H
PFLAG
Read/Write
After reset
Bit 7
NT0
R/W
-
Bit 6
NPD
R/W
-
Bit 5
LVD36
R
Bit 4
LVD24
R
Bit 3
Bit 2
C
R/W
0
Bit 1
DC
R/W
0
Bit 0
Z
R/W
0
-
-
-
0
0
Bit [7:6] NT0, NPD: Reset status flag.
NT0
NPD
Condition
Description
0
0
1
1
0
1
0
1
Watchdog reset
Reserved
Watchdog timer overflow.
-
Power on reset and LVD reset. Power voltage is lower than LVD detecting level.
External reset External reset pin detect low level status.
Finishing any reset sequence needs some time. The system provides complete procedures to make the power on reset
successful. For different oscillator types, the reset time is different. That causes the VDD rise rate and start-up time of
different oscillator is not fixed. RC type oscillator‟s start-up time is very short, but the crystal type is longer. Under client
terminal application, users have to take care the power on reset time for the master terminal requirement. The reset
timing diagram is as following.
LVD Detect Level
VDD
VSS
Power
External Reset
Watchdog Reset
System Status
VDD
VSS
External Reset
High Detect
External Reset
Low Detect
Watchdog
Overflow
Watchdog Normal Run
Watchdog Stop
System Normal Run
System Stop
Power On
Delay Time
External
Reset Delay
Time
Watchdog
Reset Delay
Time
SONiX TECHNOLOGY CO., LTD
Page 36
Version 2.0
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