SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
12 INSTRUCTION TABLE
Field
Mnemonic
Description
C
-
-
-
-
-
-
-
-
DC
Z
Cycle
MOV
A,M
M,A
A,M
M,A
A,I
-
-
-
-
-
-
-
-
-
1
1
1
1
1
A ← M
M ← A
A ← M (bank 0)
M (bank 0) ← A
A ← I
√
-
M
O
V
MOV
B0MOV
B0MOV
MOV
√
-
-
-
-
-
-
E
B0MOV
XCH
B0XCH
MOVC
M,I
A,M
A,M
1
M ← I, “M” only supports 0x80~0x87 registers (e.g. PFLAG,R,Y,Z…)
A ←→M
A ←→M (bank 0)
R, A ← ROM [Y,Z]
1+N
1+N
2
-
ADC
ADC
ADD
ADD
B0ADD
ADD
SBC
SBC
SUB
SUB
SUB
A,M
M,A
1
1+N
1
1+N
1+N
1
1
1+N
1
A ← A + M + C, if occur carry, then C=1, else C=0
M ← A + M + C, if occur carry, then C=1, else C=0
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
A
R
I
T
H
M
E
T
I
A,M A ( A + M, if occur carry, then C=1, else C=0
M,A M ( A + M, if occur carry, then C=1, else C=0
M,A M (bank 0) ( M (bank 0) + A, if occur carry, then C=1, else C=0
A,I
A,M A ( A - M - /C, if occur borrow, then C=0, else C=1
M,A M ( A - M - /C, if occur borrow, then C=0, else C=1
A,M A ( A - M, if occur borrow, then C=0, else C=1
M,A M ( A - M, if occur borrow, then C=0, else C=1
A ( A + I, if occur carry, then C=1, else C=0
1+N
1
C
A,I
A ← A - I, if occur borrow, then C=0, else C=1
AND
AND
AND
OR
OR
OR
XOR
XOR
XOR
A,M
M,A
A,I
A,M
M,A
A,I
A,M
M,A
A,I
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1+N
1
1
1+N
1
1
1+N
1
A ← A and M
M ← A and M
A ← A and I
A ← A or M
M ← A or M
A ← A or I
A ← A xor M
M ← A xor M
A ← A xor I
√
√
√
√
√
√
√
√
√
-
-
-
-
-
-
-
-
-
L
O
G
I
C
SWAP
SWAPM
RRC
RRCM
RLC
RLCM
CLR
BCLR
BSET
M
M
M
M
M
M
M
M.b
M.b
M.b
M.b
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1+N
1
1+N
1
1+N
1
1+N
1+N
1+N
1+N
A (b3~b0, b7~b4) ←M(b7~b4, b3~b0)
M(b3~b0, b7~b4) ← M(b7~b4, b3~b0)
A ← RRC M
M ← RRC M
A ← RLC M
M ← RLC M
M ← 0
M.b ← 0
M.b ← 1
P
R
O
C
E
S
S
√
√
√
√
-
-
-
-
-
B0BCLR
B0BSET
-
-
M(bank 0).b ← 0
M(bank 0).b ← 1
CMPRS
CMPRS
INCS
INCMS
DECS
DECMS
BTS0
A,I
A,M
M
M
M
-
-
-
-
-
-
-
-
-
-
-
-
1 + S
1 + S
1+ S
1+N+S
1+ S
1+N+S
1 + S
1 + S
1 + S
1 + S
2
ZF,C ← A - I, If A = I, then skip next instruction
ZF,C ← A – M, If A = M, then skip next instruction
A ← M + 1, If A = 0, then skip next instruction
M ← M + 1, If M = 0, then skip next instruction
A ← M - 1, If A = 0, then skip next instruction
M ← M - 1, If M = 0, then skip next instruction
√
√
-
-
-
-
-
-
-
√
√
-
-
-
-
-
-
-
B
R
A
N
C
H
M
M.b If M.b = 0, then skip next instruction
M.b If M.b = 1, then skip next instruction
M.b If M(bank 0).b = 0, then skip next instruction
M.b If M(bank 0).b = 1, then skip next instruction
d
d
BTS1
B0BTS0
B0BTS1
JMP
-
-
-
-
-
-
PC15/14 ← RomPages1/0, PC13~PC0 ← d
Stack ← PC15~PC0, PC15/14 ← RomPages1/0, PC13~PC0 ← d
CALL
2
M
I
S
C
RET
-
-
-
√
-
-
-
-
√
-
-
-
-
√
-
2
2
1
1
1
PC ← Stack
RETI
PUSH
POP
NOP
PC ← Stack, and to enable global interrupt
To push ACC and PFLAG (except NT0, NPD bit) into buffers.
To pop ACC and PFLAG (except NT0, NPD bit) from buffers.
No operation
Note: 1. “M” is system register or RAM. If “M” is system registers then “N” = 0, otherwise “N” = 1.
2. If branch condition is true then “S = 1”, otherwise “S = 0”.
SONiX TECHNOLOGY CO., LTD
Page 118
Version 1.1
SONIX [ SONIX TECHNOLOGY COMPANY ]
