SN8F2280 Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
9.5.11 USB ENDPOINT 4 ENABLE REGISTER
The communication with the USB host using endpoint 4, endpoint 4’s FIFO is implemented as Z bytes of dedicated
RAM. The endpoint 4 is an interrupt and bulk endpoint.
09EH
UE4R
Read/Write
After reset
Bit 7
UE4E
R/W
0
Bit 6
UE4M1
R/W
0
Bit 5
UE4M0
R/W
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
UE4E: USB endpoint 4 function enable bit.
0 = disable USB endpoint 4 function.
1 = enable USB endpoint 4 function.
Bit [6:5] UE4M [1:0]: The endpoint 4 modes determine how the SIE responds to USB traffic that the host sends to
the endpoint 4. For example, if the endpoint 4’s mode bit is set to 00 that is NAK IN/OUT mode as shown in
Table, The USB SIE will send NAK handshakes in response to any IN/OUT token set to the endpoint 4. The
bit 5 UE4M0 will auto reset to zero when the ACK transaction complete.
USB endpoint 4’s mode table
UE4M1
UE4M0
IN/OUT Token Handshake
0
0
1
1
0
1
0
1
NAK
ACK
STALL
STALL
09FH
Bit 7
Bit 6
Bit 5
UE4C5
R/W
0
Bit 4
UE4C4
R/W
0
Bit 3
UE4C3
R/W
0
Bit 2
UE4C
R/W
0
Bit 1
UE4C1
R/W
0
Bit 0
UE4C0
R/W
0
UE4R_C
Read/Write
After reset
Bit [5:0] UE4C [5:0]: Indicate the number of data bytes in a transaction: For IN transactions, firmware loads the
count with the number of bytes to be transmitted to the host from the endpoint 4 FIFO.
9.5.12 USB ENDPOINT FIFO ADDRESS SETTING REGISTER
0A0H
EP2FIFO_A
DDR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EP2FIFO7 EP2FIFO6 EP2FIFO5 EP2FIFO4 EP2FIFO3 EP2FIFO2 EP2FIFO1 EP2FIFO0
Read/Write
After reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit [7:0] EP2FIFO_ADDR [7:0]: EP2 FIFO start address.
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