SN8P1700
8-bit micro-controller build-in 12-bit ADC
INTEN INTERRUPT ENABLE REGISTER
INTEN is the interrupt request control register including four internal interrupts, three external interrupts and SIO
interrupt enable control bits. One of the register to be set “1” is to enable the interrupt request function. Once of the
interrupt occur, the program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt
service routine when the returning interrupt service routine instruction (RETI) is executed.
INTEN initial value = x000 0000
0C9H
Bit 7
Bit 6
TC1IEN
R/W
Bit 5
TC0IEN
R/W
Bit 4
T0IEN
R/W
Bit 3
SIOIEN
R/W
Bit 2
P02IEN
R/W
Bit 1
P01IEN
R/W
Bit 0
P00IEN
R/W
0
-
INTEN
P00IEN : External P0.0 interrupt control bit. 0 = disable, 1 = enable.
P01IEN : External P0.1 interrupt control bit. 0 = disable, 1 = enable.
P02IEN : External P0.2 interrupt control bit. 0 = disable, 1 = enable.
SIOIEN : SIO interrupt control bit. 0 = disable, 1 = enable.
T0IEN : T0 timer interrupt control bit. 0 = disable, 1 = enable.
TC0IEN : Timer interrupt control bit. 0 = disable, 1 = enable.
TC1IEN : Timer interrupt control bit. 0 = disable, 1 = enable.
INTRQ INTERRUPT REQUEST REGISTER
INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of
these interrupt request occurs, the bit of the INTRQ register would be set “1”. The INTRQ value needs to be clear by
programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests
occurring by the register and do the routine corresponding of the interrupt request.
INTRQ initial value = x000 0000
0C8H
INTRQ
Bit 7
0
-
Bit 6
TC1IRQ
R/W
Bit 5
TC0IRQ
R/W
Bit 4
T0IRQ
R/W
Bit 3
SIOIRQ
R/W
Bit 2
P02IRQ
R/W
Bit 1
P01IRQ
R/W
Bit 0
P00IRQ
R/W
P00IRQ : External P0.0 interrupt request bit. 0 = non-request, 1 = request.
P01IRQ : External P0.1 interrupt request bit. 0 = non-request, 1 = request.
P02IRQ : External P0.2 interrupt request bit. 0 = non-request, 1 = request.
SIOIRQ : SIO interrupt request bit. 0 = non-request, 1 = request.
T0IRQ : T0 timer interrupt request control bit. 0 = non request, 1 = request.
TC0IRQ : TC0 timer interrupt request controls bit. 0 = non request, 1 = request.
TC1IRQ : TC1 timer interrupt request controls bit. 0 = non request, 1 = request.
When interrupt occurs, the related request bit of INTRQ register will be set to “1” no matter the related enable bit of
INTEN register is enabled or disabled. If the related bit of INTEN = 1 and the related bit of INTRQ is also set to be “1”.
As the result, the system will execute the interrupt vector (ORG 8). If the related bit of INTEN = 0, moreover, the
system won’t execute interrupt vector even when the related bit of INTRQ is set to be “1”. Users need to be cautious
with the operation under multi-interrupt situation.
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