USB 2.0 HSIC Hi-Speed 4-Port Hub Controller
Datasheet
8.4
Resets
The device has the following chip level reset sources:
Power-On Reset (POR)
External Chip Reset (RESET_N)
USB Bus Reset
8.4.1
8.4.2
Power-On Reset (POR)
A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and
reapplied to the device. A timer within the device will assert the internal reset per the specifications
listed in Section 9.5.1, "Power-On Configuration Strap Valid Timing," on page 64.
External Chip Reset (RESET_N)
A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within
operating range, per the specifications in Section 9.5.2, "Reset and Configuration Strap Timing," on
page 64. While reset is asserted, the device (and its associated external circuitry) enters Standby Mode
and consumes minimal current.
Assertion of RESET_N causes the following:
1. The PHY is disabled and the differential pairs will be in a high-impedance state.
2. All transactions immediately terminate; no states are saved.
3. All internal registers return to the default state.
4. The external crystal oscillator is halted.
5. The PLL is halted.
6. The HSIC Strobe and Data pins are driven low.
Note: All power supplies must have reached the operating levels mandated in Section 9.2, "Operating
Conditions**," on page 59, prior to (or coincident with) the assertion of RESET_N.
8.4.3
USB Bus Reset
In response to the upstream port signaling a reset to the device, the device performs the following:
Note: The device does not propagate the upstream USB reset to downstream devices.
1. Sets default address to 0.
2. Sets configuration to: Unconfigured.
3. Moves device from suspended to active (if suspended).
4. Complies with Section 11.10 of the USB 2.0 Specification for behavior after completion of the
reset sequence.
The host then configures the device in accordance with the USB Specification.
8.5
Link Power Management (LPM)
The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states per
the USB 2.0 Link Power Management Addendum. These supported LPM states offer low transitional
Revision 1.0 (06-17-13)
56
SMSC USB4604
DATASHEET
SMSC [ SMSC CORPORATION ]
