USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 9.8 SPI Timing Values (60 MHz Operation)
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tfc
tceh
tclq
tdh
Clock frequency
60
MHz
ns
Chip enable (SPI_CE_EN) high time
Clock to input data
50
9
ns
Input data hold time
0
5
ns
tos
Output setup time
ns
toh
tov
tcel
tceh
Output hold time
5
ns
Clock to output valid
4
ns
Chip enable (SPI_CE_EN) low to first clock
Last clock to chip enable (SPI_CE_EN) high
12
12
ns
ns
9.6
Clock Specifications
The device can accept a 24 MHz single-ended clock oscillator input. REFCLK should be driven with a
clock that adheres to the specifications outlined in Section 9.6.1, "External Reference Clock
(REFCLK)".
9.6.1
External Reference Clock (REFCLK)
The following input clock specifications are suggested:
50% duty cycle 10%
350 PPM
The input frequency of REFCLK is user configurable. Refer to Section 8.4, "Reference Clock" for
additional information on configuring a reference clock input.
Note: The external clock is recommended to conform to the signalling levels designated in the
JEDEC specification on 1.2V CMOS Logic.
SMSC USB3813
65
Revision 1.0 (06-17-13)
DATASHEET
SMSC [ SMSC CORPORATION ]
