Integrated USB 2.0 Compatible 7-Port Hub
Datasheet
5.3.4
Slave Device Time-Out
According to the SMBus Specification, V1.0 devices in a transfer can abort the transfer in progress
and release the bus when any single clock low interval exceeds 25ms (TTIMEOUT, MIN). Devices that
have detected this condition must reset their communication and be able to receive a new START
condition no later than 35ms (TTIMEOUT, MAX).
Note: Some simple devices do not contain a clock low drive circuit; this simple kind of device typically
resets its communications port after a start or stop condition.
5.3.5
5.3.6
5.3.7
Stretching the SCLK Signal
The Hub supports stretching of the SCLK by other devices on the SMBus. The Hub does not stretch
the SCLK.
SMBus Timing
The SMBus Slave Interface complies with the SMBus AC Timing Specification. See the SMBus timing
in the “Timing Diagram” section.
Bus Reset Sequence
The SMBus Slave Interface resets and returns to the idle state upon a START field followed
immediately by a STOP field.
5.3.8
5.3.9
SMBus Alert Response Address
The SMBALERT# signal is not supported by the Hub.
Internal SMBus Memory Register Set
The following table provides the SMBus slave interface register map values.
Table 5.4 SMBus Slave Interface Register Map
REG
ADDR
BIT 7
(MSB)
BIT 0
(LSB)
R/W
REGISTER NAME
ABBR
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Status/Command
VID LSB
STCD
VIDL
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
VID MSB
VIDM
PIDL
PID LSB
PID MSB
PIDM
DIDL
DIDM
CFG1
CFG2
NRD
DID LSB
DID MSB
Config Data Byte 1
Config Data Byte 2
Non-Removable
Devices
0Ah
0Bh
R/W
R/W
Port Disable (Self)
Port Disable (Bus)
PDS
PDB
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
Revision 2.3 (08-27-07)
SMSC USB2507
DATA2S6HEET
SMSC [ SMSC CORPORATION ]
