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SP37E760 参数 Datasheet PDF下载

SP37E760图片预览
型号: SP37E760
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 V的I / O控制器的嵌入式应用 [3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS]
分类和应用: 控制器
文件页数/大小: 78 页 / 507 K
品牌: SMSC [ SMSC CORPORATION ]
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6
AUTO POWER MANAGEMENT  
Power management is provided for the following SP37E760 logical devices: UART1, UART2 and the Parallel Port.  
For each logical device two types of power management are provided; direct powerdown and auto powerdown.  
Direct powerdown is controlled by the powerdown bits in the configuration registers. One bit is provided for each  
logical device. Auto powerdown can be enabled for each logical device by setting the Auto Powerdown Enable bits in  
the configuration registers. In addition, a chip-level hardware powerdown function has been provided through the  
PWRGD pin. Refer to Table 1 and to other descriptions of the PWRGD function, for example section  
CONFIGURATION, for more information.  
6.1 Pin Behavior  
The SP37E760 is specifically designed for portable PC systems where power conservation is a primary concern.  
Consequently, the behavior of the device pins during powerdown are very important.  
6.1.1 SYSTEM INTERFACE PINS  
Table 22 gives the state of the system interface pins in the powerdown state. Pins unaffected by the powerdown are  
labeled “Unchanged”. Input pins are “Disabled” to prevent them from causing currents internal to the SP37E760  
when they have indeterminate input values.  
Table 22 - State of System Pins in Auto Powerdown  
SYSTEM PINS  
STATE IN AUTO POWERDOWN  
Input Pins  
IOR  
IOW  
Unchanged  
Unchanged  
A[0:9]  
D[0:7]  
RESET  
IDENT  
DACK  
TC  
Unchanged  
Unchanged  
Unchanged  
Unchanged  
Unchanged  
Unchanged  
Output Pins  
Unchanged (low)  
Unchanged  
FINTR  
DB[0:7]  
FDRQ  
Unchanged (low)  
6.2 UART Power Management  
Direct UART power management is controlled by the UART1 and UART2 Power Down bits in Configuration Register  
2. Refer to section CR02 on page 49 for more information.  
UART Auto Power Management is enabled by the UART 1 and UART 2 Enable bits in Configuration Register 7 (see  
section CR07 on page 51). When set, these bits enable the following auto power management features:  
1. The transmitter enters auto powerdown when the transmit buffer and transmit shift register are empty.  
2. The receiver enters powerdown when the following conditions are all met:  
ƒ
ƒ
Receive FIFO is empty  
The receiver is waiting for a start bit.  
Note: While in the powerdown state, the Ring Indicator interrupts are still valid and are activated when the RI  
inputs change.  
The UART transmitters exit the powerdown state on a write to the XMIT buffer. The UART receivers exit the auto  
powerdown state when RXDx changes state.  
SMSC DS – SP37E760  
Page 43  
Rev. 04/13/2001  
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