Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PCI_CLK
SER_IRQ
t1
t2
Figure 13.20 – Setup and Hold Time
NAME
t1
t2
DESCRIPTION
SER_IRQ Setup Time to PCI_CLK Rising
SER_IRQ Hold Time to PCI_CLK Rising
MIN
7
0
TYP
MAX
UNITS
nsec
nsec
Data
Stop (1-2 Bits)
Data (5-8 Bits)
Start
Parity
t1
TXD
Figure 13.21 – Serial Port Data
NAME
t1
DESCRIPTION
Serial Port Data Bit Time
MIN
TYP
tBR
MAX
UNITS
nsec
1
Note 1: tBR is 1/Baud Rate. The Baud Rate is programmed through the divisor latch registers. Baud Rates have
percentage errors indicated in the “Baud Rate” table in the “Serial Port” section.
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
212
SMSC LPC47M182
DATASHEET
SMSC [ SMSC CORPORATION ]
