REGISTER
ADDRESS*
REGISTER
SYMBOL
REGISTER NAME
BIT 0
BIT 1
Delta Clear
ADDR = 6
MODEM Status Register
MSR
Delta Data
Set Ready
(DDSR)
to Send
(DCTS)
ADDR = 7
Scratch Register (Note 4)
Divisor Latch (LS)
SCR
DDL
Bit 0
Bit 0
Bit 1
Bit 1
ADDR = 0
DLAB = 1
ADDR = 1
DLAB = 1
Divisor Latch (MS)
DLM
Bit 8
Bit 9
*DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
Table 33 – Register Summary for an Individual UART Channel (continued)
BIT 2
Data Bit 2
Data Bit 2
BIT 3
Data Bit 3
Data Bit 3
BIT 4
Data Bit 4
Data Bit 4
0
BIT 5
Data Bit 5
Data Bit 5
0
BIT 6
Data Bit 6
Data Bit 6
0
BIT 7
Data Bit 7
Data Bit 7
0
Enable
Enable
MODEM
Status
Receiver Line
Status
Interrupt
(ELSI)
Interrupt
(EMSI)
FIFOs
Interrupt ID Bit Interrupt ID Bit 0
(Note 5)
0
FIFOs
Enabled
(Note 5)
Enabled
(Note 5)
XMIT
Reset
FIFO DMA
Select (Note
6)
Mode Reserved
Reserved
RCVR Trigger RCVR Trigger
LSB
MSB
Divisor Latch
Number
Stop
of Parity Enable Even
Parity Stick Parity
Set Break
Access
(DLAB)
Bit
Bits (PEN)
Select (EPS)
(STB)
OUT1
OUT2
Loop
0
0
0
(Note 3)
(Note 3)
Parity
(PE)
Error Framing Error Break
(FE)
Transmitter
Transmitter
Error in RCVR
Interrupt (BI)
Holding
Register
(THRE)
Empty (TEMT) FIFO (Note 5)
(Note 2)
Data Carrier
Detect (DCD)
Trailing Edge Delta
Data Clear to Send Data
Set Ring Indicator
Ring Indicator Carrier Detect (CTS)
Ready (DSR) (RI)
(TERI)
Bit 2
(DDCD)
Bit 3
Bit 4
Bit 4
Bit 12
Bit 5
Bit 5
Bit 13
Bit 6
Bit 6
Bit 14
Bit 7
Bit 7
Bit 15
Bit 2
Bit 3
Bit 10
Bit 11
Note 3: This bit no longer has a pin associated with it.
Note 4: When operating in the XT mode, this register is not available.
Note 5: These bits are always zero in the non-FIFO mode.
Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.
Note 7: The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register (runtime
register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x21).
SMSC DS – LPC47M14X
Page 70
Rev. 03/19/2001
SMSC [ SMSC CORPORATION ]
