Table 30 – Interrupt Control Table
FIFO
MODE
ONLY
INTERRUPT
IDENTIFICATION
REGISTER
INTERRUPT SET AND RESET FUNCTIONS
INTERRUPT
PRIORITY INTERRUPT
INTERRUPT
SOURCE
RESET
LEVEL
TYPE
BIT 3
BIT 2 BIT 1 BIT 0
CONTROL
0
0
0
1
-
None
None
-
Overrun Error,
Receiver Line
Status
Parity Error,
Reading the Line
Status Register
0
1
1
0
Highest
Framing Error or
Break Interrupt
Read Receiver
Buffer or the FIFO
drops below the
trigger level.
Received Data
Available
Receiver Data
Available
0
1
1
0
0
0
0
Second
No Characters
Have Been
Removed From or
Input to the RCVR
FIFO during the
last 4 Char times
and there is at
Character
Timeout
Reading the
Receiver Buffer
Register
1
Second
Indication
least 1 char in it
during this time
Reading the IIR
Register (if Source
of Interrupt) or
Writing the
Transmitter
Holding
Transmitter
Holding Register
Empty
0
0
0
0
1
0
0
0
Third
Register Empty
Transmitter
Holding Register
Clear to Send or
Data Set Ready or
Ring Indicator or
Data Carrier
Reading the
MODEM Status
Register
MODEM
Status
Fourth
Detect
LINE CONTROL REGISTER (LCR)
Address Offset = 3H, DLAB = 0, READ/WRITE
Start LSB Data 5-8 bits MSB Parity Stop
Serial Data
This register contains the format information of the serial line. The bit definitions are:
Bits 0 and 1
These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and 1
is as follows:
The Start, Stop and Parity bits are not included in the word length.
BIT 1
BIT 0 WORD LENGTH
0
0
1
1
0
1
0
1
5 Bits
6 Bits
7 Bits
8 Bits
SMSC DS – LPC47M14X
Page 63
Rev. 05/02/2000
SMSC [ SMSC CORPORATION ]
