Table 65 – I/O Base Address Configuration Register Description
BASE I/O
LOGICAL
DEVICE
NUMBER
0x00
LOGICAL
DEVICE
FDC
REGISTER
RANGE
FIXED
INDEX
0x60,0x61
(NOTE 1)
[0x0100:0x0FF8]
BASE OFFSETS
+0 : SRA
+1 : SRB
ON 8 BYTE BOUNDARIES +2 : DOR
+3 : TSR
+4 : MSR/DSR
+5 : FIFO
+7 : DIR/CCR
n/a
n/a
0x01
0x02
0x03
Reserved
Reserved
Parallel
Port
n/a
n/a
0x60,0x61
n/a
n/a
[0x0100:0x0FFC]
+0 : Data/ecpAfifo
ON 4 BYTE BOUNDARIES +1 : Status
(EPP Not supported)
or
[0x0100:0x0FF8]
+2 : Control
+400h : cfifo/ecpDfifo/tfifo/cnfgA
+401h : cnfgB
ON 8 BYTE BOUNDARIES +402h : ecr
(all modes supported,
+3 : EPP Address
EPP is only available when +4 : EPP Data 0
the base address is on an 8-
byte boundary)
+5 : EPP Data 1
+6 : EPP Data 2
+7 : EPP Data 3
+0 : RB/TB/LSB div
+1 : IER/MSB div
0x04
0x05
Serial Port 1
Serial Port 2
0x60,0x61
0x60,0x61
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES +2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
+0 : RB/TB/LSB div
+1 : IER/MSB div
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES +2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
0x06
0x07
Reserved
KYBD
n/a
n/a
n/a
n/a
Not Relocatable
+0 : Data Register
Fixed Base Address: 60,64 +4 : Command/Status Reg.
0x08
0x09
Reserved
Game Port
n/a
0x60,0x61
n/a
n/a
[0x0100:0x0FFF]
on 1 byte boundaries
[0x0000:0x0F7F]
on 128-byte boundaries
+00: Game Port Register
0x0A
Runtime
Register
Block
0x60,0x61
+00 : PME Status
.
.
.
+5F : Keyboard Scan Code
(See Table in “Runtime Registers”
section for Full List)
SMSC DS – LPC47M14X
Page 161
Rev. 03/19/2001
SMSC [ SMSC CORPORATION ]
