REGISTER
TEST 3
ADDRESS
DESCRIPTION
STATE
0x2F R/W Test Modes: Reserved for SMSC. Users should not
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write to this register, may produce undesired results.
Default = 0x00, on
VCC POR and
VTR POR
Note 1: CR22 Bit 5 is reset by VTR POR only.
Note 2:
To allow the selection of the configuration address to a user defined location, these Configuration Address
Bytes are used. There is no restriction on the address chosen, except that A0 is 0, that is, the address must be on an
even byte boundary. As soon as both bytes are changed, the configuration space is moved to the specified location with
no delay (Note: Write byte 0, then byte 1; writing CR27 changes the base address).
The configuration address is only reset to its default address upon a Hard Reset or Vcc POR.
Note: The default configuration address is either 02E or 04E, as specified by the SYSOPT pin.
Logical Device Configuration/Control Registers [0x30-0xFF]
Used to access the registers that are assigned to each logical unit. This chip supports nine logical units and has nine
sets of logical device registers. The nine logical devices are Floppy, Parallel, Serial 1, Serial 2, Keyboard Controller,
game port, PME, MPU-401, and USB Hub. A separate set (bank) of control and configuration registers exists for each
logical device and is selected with the Logical Device # Register (0x07).
The INDEX PORT is used to select a specific logical device register. These registers are then accessed through the
DATA PORT.
The Logical Device registers are accessible only when the device is in the Configuration State. The logical register
addresses are shown in the table below.
Table 63 – Logical Device Registers
LOGICAL DEVICE
REGISTER
ADDRESS
DESCRIPTION
Bits[7:1] Reserved, set to zero.
Bit[0]
STATE
Activate (Note 1)
(0x30)
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Default = 0x00
= 1
Activates the logical device currently
selected through the Logical Device #
register.
on VCC POR, VTR POR,
HARD RESET and
= 0
Logical device currently selected is
SOFT RESET
inactive
Logical Device Control
Logical Device Control
(0x31-0x37) Reserved – Writes are ignored, reads return 0.
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C
(0x38-0x3F) Vendor Defined - Reserved - Writes are
ignored, reads return 0.
Memory Base Address
I/O Base Address (Note 2) (0x60-0x6F) Registers 0x60 and 0x61 set the base address
(0x40-0x5F) Reserved – Writes are ignored, reads return 0.
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for the device. If more than one base address
is required, the second base address is set by
(see Device Base I/O
Address Table)
0x60,2,... =
addr[15:8]
registers 0x62 and 0x63.
Refer to Table 65 for the number of base
address registers used by each device.
Default = 0x00
0x61,3,... =
addr[7:0]
Unused registers will ignore writes and return
zero when read.
on VCC POR, VTR POR,
HARD RESET and
SOFT RESET
SMSC DS – LPC47M14X
Page 159
Rev. 03/19/2001
SMSC [ SMSC CORPORATION ]
