6.13.9 Latches On Keyboard and Mouse IRQs
The implementation of the latches on the keyboard and mouse interrupts is shown below.
KLATCH Bit
VCC
D
KINT
new
Q
KINT
CLR
8042
RD 60
FIGURE 6 – KEYBOARD LATCH
MLATCH Bit
VCC
MINT
new
D
Q
MINT
CLR
8042
RD 60
FIGURE 7 – MOUSE LATCH
The KLATCH and MLATCH bits are located in the KRST_GA20 register, in Logical Device 7 at 0xF0.
These bits are defined as follows:
Bit[4]: MLATCH – Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ANDed with Latched MINT
(default), 1=MINT is the latched 8042 MINT.
Bit[3]: KLATCH – Keyboard Interrupt latch control bit. 0=KINT is the 8042 KINT ANDed with Latched
KINT (default), 1=KINT is the latched 8042 KINT.
See the “Configuration” section for a description of this register.
SMSC DS – LPC47M14X
Page 108
Rev. 03/19/2001
SMSC [ SMSC CORPORATION ]
