1. ECP is not enabled in the configuration registers.
SPP, PS/2 Parallel port or EPP mode is selected through ecr while in ECP mode.
2
Exit Auto Powerdown
The parallel port logic can change powerdown modes when the ECP mode is changed through the ecr
register or when the parallel port mode is changed through the configuration registers.
SERIAL IRQ
The LPC47B27x supports the serial interrupt to transmit interrupt information to the host system. The
serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.
Timing Diagrams for SER_IRQ Cycle
A) Start Frame timing with source sampled a low pulse on IRQ1
START FRAME
IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME
SL
or
H
R
T
S
R
T
S
R
T
S
R
T
H
PCI_CLK
1
START
SER_IRQ
Drive Source
IRQ1
Host Controller
None
IRQ1
None
Note:
H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample
Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI
bridge hierarchy in a synchronous bridge design.
B) Stop Frame Timing with Host using 17 SER_IRQ sampling period.
IRQ14
FRAME
R
IRQ15
FRAME
R
IOCHCK#
FRAME
STOP FRAME
NEXT CYCLE
START
2
S
T
S
T
S
R
T
H
R
T
I
PCI_CLK
SER_IRQ
Driver
1
3
STOP
None
IRQ15
None
Host Controller
Note:
H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle
Note 1: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn-
around clock of the Stop Frame.
Note 2: There may be none, one or more Idle states during the Stop Frame.
Note 3: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
SER_IRQ Cycle Control
There are two modes of operation for the SER_IRQ Start Frame.
1) Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one
clock, while the SER_IRQ is Idle. After driving low for one clock the SER_IRQ must immediately be tri-
stated without at any time driving high. A Start Frame may not be initiated while the SER_IRQ is Active.
The SER_IRQ is Idle between Stop and Start Frames. The SER_IRQ is Active between Start and Stop
Frames. This mode of operation allows the SER_IRQ to be Idle when there are no IRQ/Data transitions
which should be most of the time.
SMSC LPC47B27x
- 97 -
Rev. 08-10-04
DATASHEET
SMSC [ SMSC CORPORATION ]
