High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
6.9
EEPROM Timing
The following specifies the EEPROM timing requirements for the LAN9218
Figure 6.7 EEPROM Timing
Table 6.10 EEPROM Timing Values
SYMBOL
DESCRIPTION
EECLK Cycle time
MIN
TYP
MAX
UNITS
tCKCYC
tCKH
1110
550
550
1070
30
1130
570
570
ns
ns
ns
ns
ns
ns
EECLK High time
tCKL
EECLK Low time
tCSHCKH
tCKLCSL
tDVCKH
EECS high before rising edge of EECLK
EECLK falling edge to EECS low
EEDIO valid before rising edge of EECLK
(OUTPUT)
550
tCKHDIS
EEDIO disable after rising edge EECLK
(OUTPUT)
550
ns
tDSCKH
tDHCKH
EEDIO setup to rising edge of EECLK (INPUT)
90
0
ns
ns
EEDIO hold after rising edge of EECLK
(INPUT)
tCKLDIS
tCSHDV
tDHCSL
tCSL
EECLK low to data disable (OUTPUT)
EEDIO valid after EECS high (VERIFY)
EEDIO hold after EECS low (VERIFY)
EECS low
580
ns
ns
ns
ns
600
0
1070
Revision 1.5 (07-18-06)
124
SMSC LAN9218
DATASHEET
SMSC [ SMSC CORPORATION ]
