High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
5.3.3
INT_STS—Interrupt Status Register
Offset:
58h
Size:
32 bits
This register contains the current status of the generated interrupts. Writing a 1 to the corresponding
bits acknowledges and clears the interrupt.
BITS
DESCRIPTION
TYPE
DEFAULT
31
Software Interrupt (SW_INT). This interrupt is generated when the
SW_INT_EN bit is set high. Writing a one clears this interrupt.
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0
30-26
25
Reserved
RO
-
TX Stopped (TXSTOP_INT). This interrupt is issued when STOP_TX bit
in TX_CFG is set, and the transmitter is halted.
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0
24
23
RX Stopped (RXSTOP_INT). This interrupt is issued when the receiver is
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0
0
halted.
RX Dropped Frame Counter Halfway (RXDFH_INT). This interrupt is
issued when the RX Dropped Frames Counter counts past its halfway
point (7FFFFFFFh to 80000000h).
22
21
Reserved
RO
0
0
TX IOC Interrupt (TX_IOC). When a buffer with the IOC flag set has
finished being loaded into the TX FIFO, this interrupt is generated.
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20
19
RX DMA Interrupt (RXD_INT). This interrupt is issued when the amount
of data programmed in the RX DMA Count (RX_DMA_CNT) field of the
RX_CFG register has been transferred out of the RX FIFO.
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0
0
GP Timer (GPT_INT). This interrupt is issued when the General Purpose
timer wraps past zero to FFFFh.
18
17
PHY (PHY_INT). Indicates a PHY Interrupt event.
RO
0
0
Power Management Event Interrupt (PME_INT). This interrupt is issued
when a Power Management Event is detected as configured in the
PMT_CTRL register. This interrupt functions independent of the PME
signal, and will still function if the PME signal is disabled. Writing a '1'
clears this bit regardless of the state of the PME hardware signal.
Notes:
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Detection of a Power Management Event, and assertion of the PME
signal will not wakeup the LAN9218i. The LAN9218i will only wake up
when it detects a host write cycle of any data to the BYTE_TEST
register.
The Interrupt Deassertion interval does not apply to the PME interrupt.
16
15
14
TX Status FIFO Overflow (TXSO). Generated when the TX Status
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0
0
0
FIFO overflows.
Receive Watchdog Time-out (RWT). Interrupt is generated when a
packet larger than 2048 bytes has been received.
Receiver Error (RXE). Indicates that the receiver has encountered an
error. Please refer to Section 3.12.5, "Receiver Errors," on page 56 for a
description of the conditions that will cause an RXE.
13
Transmitter Error (TXE). When generated, indicates that the
transmitter has encountered an error. Please refer to Section 3.11.8,
"Transmitter Errors," on page 51, for a description of the conditions that
will cause a TXE.
R/WC
0
Revision 1.8 (06-06-07)
72
SMSC LAN9218i
DATASHEET
SMSC [ SMSC CORPORATION ]
