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LAN9218I_07 参数 Datasheet PDF下载

LAN9218I_07图片预览
型号: LAN9218I_07
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能单芯片10/100以太网控制器,带有HP Auto-MDIX的和工业温度支持 [High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support]
分类和应用: 控制器以太网局域网(LAN)标准
文件页数/大小: 133 页 / 1530 K
品牌: SMSC [ SMSC CORPORATION ]
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High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support  
Datasheet  
5.3.1  
ID_REV—Chip ID and Revision  
Offset:  
50h  
Size:  
32 bits  
This register contains the ID and Revision fields for this design.  
BITS  
31-16  
15-0  
DESCRIPTION  
Chip ID. This read-only field identifies this design  
Chip Revision  
TYPE  
RO  
DEFAULT  
118Ah  
RO  
0000h  
5.3.2  
IRQ_CFG—Interrupt Configuration Register  
Offset:  
54h  
Size:  
32 bits  
This register configures and indicates the state of the IRQ signal.  
BITS  
DESCRIPTION  
TYPE  
DEFAULT  
31:24  
Interrupt Deassertion Interval (INT_DEAS). This field determines the  
Interrupt Request Deassertion Interval in multiples of 10 microseconds.  
R/W  
0
Setting this field to zero causes the device to disable the INT_DEAS  
Interval, reset the interval counter, and issue any pending interrupts. If a  
new, non-zero value is written to this field, any subsequent interrupts will  
obey the new setting.  
Note:  
This field does not apply to the PME interrupt.  
23-15  
14  
Reserved  
RO  
SC  
-
Interrupt Deassertion Interval Clear (INT_DEAS_CLR). Writing a one  
to this register clears the de-assertion counter in the IRQ Controller, thus  
causing a new de-assertion interval to begin (regardless of whether or  
not the IRQ Controller is currently in an active de-assertion interval).  
0
13  
12  
Interrupt Deassertion Status (INT_DEAS_STS). When set, this bit  
indicates that interrupts are currently in a deassertion interval, and will  
not be delivered to the IRQ pin. When this bit is clear, interrupts are not  
currently in a deassertion interval, and will be delivered to the IRQ pin.  
SC  
RO  
0
0
Master Interrupt (IRQ_INT). This read-only bit indicates the state of the  
internal IRQ line, regardless of the setting of the IRQ_EN bit, or the state  
of the interrupt de-assertion function. When this bit is high, one of the  
enabled interrupts is currently active.  
11-9  
8
Reserved  
RO  
-
IRQ Enable (IRQ_EN) – This bit controls the final interrupt output to the  
IRQ pin. When clear, the IRQ output is disabled and permanently  
deasserted. This bit has no effect on any internal interrupt status bits.  
R/W  
0
7-5  
Reserved  
RO  
-
Revision 1.8 (06-06-07)  
70  
SMSC LAN9218i  
DATASHEET