High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
Table 2.5 System and Power Signals (continued)
PIN
NO.
BUFFER
TYPE
NUM
PINS
NAME
SYMBOL
DESCRIPTION
3,65
Core Voltage
Decoupling
VDD_CORE
P
2
+1.8 V from internal core regulator.
Both pins must be connected
together externally. Each pin requires
a 0.01uF decoupling capacitor. In
addition, pin 3 requires a bulk 10uF
capacitor (<2 Ohm ESR) in parallel.
See Note 2.1.
1,66
7
Core Ground
PLL Power
GND_CORE
VDD_PLL
P
P
2
1
Ground for internal digital logic
+1.8V Power from the internal PLL
regulator. This pin must be connected
to a 10uF capacitor (<2 Ohm ESR), in
parallel with a 0.01uF capacitor to
ground. See Note 2.1.
4
8
PLL Ground
VSS_PLL
VDD_REF
P
P
1
1
GND for the PLL
Reference Power
Connected to 3.3v power and used
as the reference voltage for the
internal PLL
11
Reference Ground
VSS_REF
P
1
Ground for internal PLL reference
voltage
Note 2.1 Please refer to the SMSC application note AN14.10 - “Migrating from LAN9118 to the
LAN9218I” for additional details.
2.1
Buffer Types
Table 2.6 Buffer Types
TYPE
DESCRIPTION
Input pin
I
IS
Schmitt triggered Input
Output with 12mA sink and 12mA source
Open-drain output with 12mA sink
I/O with 8mA symmetrical drive
Open-drain output with 8mA sink
Output 8mA symmetrical drive
50uA (typical) internal pull-up
50uA (typical) internal pull-down
Analog input
O12
OD12
IO8
OD8
O8
PU
PD
AI
Analog output
AO
Revision 1.8 (06-06-07)
20
SMSC LAN9218i
DATASHEET
SMSC [ SMSC CORPORATION ]
