High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
1.11
Host Bus Interface (SRAM Interface)
The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as
an interface for the LAN9218i Control and Status Registers (CSR’s).
The host bus interface is the primary bus for connection to the embedded host system. This interface
models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface.
Programmed I/O transactions are supported.
The LAN9218i host bus interface supports 32-bit and 16-bit bus transfers. Internally, all data paths are
32-bits wide. The LAN9218i can be interfaced to either Big-Endian or Little-Endian processors.
SMSC LAN9218i
13
Revision 1.8 (06-06-07)
DATASHEET
SMSC [ SMSC CORPORATION ]
