High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and
deasserted in any order.
6.6
PIO Writes
PIO writes are used for all LAN9218i write cycles. PIO writes can be performed using Chip Select
(nCS) or Write Enable (nWR). Either or both of these control signals must go high between cycles for
the period specified.
PIO Writes are valid for 16- and 32-bit access. Timing for 16-bit and 32-bit PIO write cycles are
identical with the exception that D[31:16] are ignored during a 16-bit write.
A[7:1]
nCS, nWR
Data Bus
Figure 6.5 PIO Write Cycle Timing
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths.
Table 6.7 PIO Write Cycle Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tcycle
tcsl
Write Cycle Time
45
32
13
0
ns
ns
ns
ns
ns
ns
ns
nCS, nWR Assertion Time
nCS, nWR Deassertion Time
Address Setup to nCS, nWR Assertion
Address Hold Time
tcsh
tasu
tah
0
tdsu
tdh
Data Setup to nCS, nWR Deassertion
Data Hold Time
7
0
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
Revision 1.8 (06-06-07)
122
SMSC LAN9218i
DATASHEET
SMSC [ SMSC CORPORATION ]
