High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
6.4
RX Data FIFO Direct PIO Reads
In this mode the upper address inputs are not decoded, and any read of the LAN9218i will read the
RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is
normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9218i. Timing is
identical to a PIO read, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Timing for 16-bit and 32-bit Direct PIO Read cycles is identical with the exception that D[31:16] is not
driven during a 16-bit read. Note that address lines A[2:1] are still used, and address bits A[7:3] are
ignored.
FIFO_SEL
A[2:1]
nCS, nRD
Data Bus
Figure 6.3 RX Data FIFO Direct PIO Read Cycle Timing
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Table 6.5 RX Data FIFO Direct PIO Read Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tcycle
tcsl
Read Cycle Time
45
32
13
ns
ns
ns
ns
ns
ns
ns
ns
ns
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address, FIFO_SEL Setup to nCS, nRD Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
tcsh
tcsdv
tasu
tah
30
0
0
0
tdon
tdoff
tdoh
7
0
Note: An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The
cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and de-
asserted in any order.
Revision 1.8 (06-06-07)
120
SMSC LAN9218i
DATASHEET
SMSC [ SMSC CORPORATION ]
