16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
5.4
MAC Control and Status Registers
These registers are located in the MAC module and are accessed indirectly through the MAC-CSR
synchronizer port. Table 5.6, "MAC CSR Register Map", shown below, lists the MAC registers that are
accessible through the indexing method using the MAC_CSR_CMD and MAC_CSR_DATA registers
(see sections MAC_CSR_CMD – MAC CSR Synchronizer Command Register and MAC_CSR_DATA
– MAC CSR Synchronizer Data Register).
Table 5.6 MAC CSR Register Map
MAC CONTROL AND STATUS REGISTERS
INDEX
SYMBOL
MAC_CR
ADDRH
ADDRL
HASHH
HASHL
MII_ACC
MII_DATA
FLOW
REGISTER NAME
MAC Control Register
DEFAULT
00040000h
0000FFFFh
FFFFFFFFh
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
1
2
3
4
5
6
7
8
9
A
B
C
MAC Address High
MAC Address Low
Multicast Hash Table High
Multicast Hash Table Low
MII Access
MII Data
Flow Control
VLAN1
VLAN1 Tag
VLAN2
VLAN2 Tag
WUFF
Wake-up Frame Filter
Wake-up Control and Status
WUCSR
SMSC LAN9217
99
Revision 1.8 (06-06-07)
DATASHEET
SMSC [ SMSC CORPORATION ]
