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LAN9217_07 参数 Datasheet PDF下载

LAN9217_07图片预览
型号: LAN9217_07
PDF下载: 下载PDF文件 查看货源
内容描述: 16位高性能单芯片10/100以太网控制器与HP Auto-MDIX的 [16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX]
分类和应用: 控制器以太网局域网(LAN)标准
文件页数/大小: 137 页 / 1566 K
品牌: SMSC [ SMSC CORPORATION ]
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16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX  
Datasheet  
5.4.3  
ADDRL—MAC Address Low Register  
Offset:  
3
Attribute:  
Size:  
R/W  
Default Value:  
FFFFFFFFh  
32 bits  
The MAC Address Low register contains the lower 32 bits of the physical address of the MAC. The  
contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM  
Controller if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0])  
is loaded from address 0x01 of the EEPROM. The most significant byte of this register is loaded from  
address 0x04 of the EEPROM. Please refer to Section 4.6 for more information on the EEPROM.  
BITS  
31-0  
DESCRIPTION  
Physical Address [31:0]. This field contains the lower 32 bits (31:0) of the Physical Address of the  
LAN9217 device. The content of this field is undefined until loaded from the EEPROM at power-on.  
The host can update the contents of this field after the initialization process has completed.  
Table 5.7 below illustrates the byte ordering of the ADDRL and ADDRH registers with respect to the  
reception of the Ethernet physical address. Also shown is the correlation between the EEPROM  
addresses and ADDRL and ADDRH registers.  
Table 5.7 ADDRL, ADDRH and EEPROM Byte Ordering  
ORDER OF RECEPTION ON  
EEPROM ADDRESS  
ADDRN  
ETHERNET  
0x01  
0x02  
0x03  
0x04  
0x05  
0x06  
ADDRL[7:0]  
ADDRL[15:8]  
ADDRL[23:16]  
ADDRL[31:24]  
ADDRH[7:0]  
ADDRH[15:8]  
1st  
2nd  
3rd  
4th  
5th  
6th  
As an example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the ADDRL and  
ADDRH registers would be programmed as shown in Figure 5.2. The values required to automatically  
load this configuration from the EEPROM are also shown.  
31  
24 23  
16 15  
0xBC  
8
7
0
0xBC  
0x9A  
0x78  
0x56  
0x34  
0x12  
0xA5  
0x06  
0x05  
0x04  
0x03  
0x02  
0x01  
0x00  
xx  
xx  
0x9A  
ADDRH  
16 15  
31  
24 23  
8 7  
0
0x78  
0x56  
0x34  
0x12  
EEPROM  
ADDRL  
Figure 5.2 Example ADDRL, ADDRH and EEPROM Setup  
Note: By convention, the left most byte of the Ethernet address (in this example 0x12) is the most  
significant byte and is transmitted/received first.  
SMSC LAN9217  
103  
Revision 1.8 (06-06-07)  
DATASHEET