16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
BITS
DESCRIPTION
TYPE
DEFAULT
3
External PHY Detect (EXT_PHY_DET). This bit reflects the latched value
of the EXT_PHY_DET strap. The EXT_PHY_DET strap is used to indicate
the presence of an external PHY. This strap is latched from the value of the
external MDIO signal upon power-up or hard reset. If MDIO is pulled high a
‘1’ will be seen in this bit. If MDIO is pulled low a ‘0’ will be seen in this bit.
The RXT_PHY_DET strap has no other effect on the internal logic. Its only
function is to give the system designer a mechanism to indicate the
presence of an external PHY to a software application.
Dependant
on
EXT_PHY_D
ET strap pin
RO
2
External PHY Enable (EXT_PHY_EN). When set to a ‘1’, this bit enables
the external MII port. When cleared, the internal PHY is enabled and the
external MII port is disabled.
0
RW
Notes:
This signal does not control multiplexing of the SMI port or the TX_CLK
or RX_CLK signals.
There are restrictions on the use of this bit. Please refer to Section 3.11,
"MII Interface - External MII Switching," on page 41 for details.
1
0
Soft Reset Timeout (SRST_TO). If a software reset is attempted when the
internal PHY is not in the operational state (RX_CLK and TX_CLK running), the reset
will not complete and the soft reset operation will timeout and this bit will be set to a
‘1’. The host processor must correct the problem and issue another soft reset.
RO
SC
0
0
Soft Reset (SRST). Writing 1 generates a software initiated reset. This reset
generates a full reset of the MAC CSR’s. The SCSR’s (system command
and status registers) are reset except for any NASR bits. Soft reset also
clears any TX or RX errors (TXE/RXE). This bit is self-clearing.
Notes:
Do not attempt a soft reset unless the internal PHY is fully awake and
operational. After a PHY reset, or when returning from a reduced power
state, the PHY must given adequate time to return to the operational state
before a soft reset can be issued. The internal RX_CLK and TX_CLK
signals must be running for a proper software reset. Please refer to
Section 6.8, "Reset Timing," on page 128 for details on PHY reset timing.
The LAN9217 must always be read at least once after power-up, reset, or
upon return from a power-saving state or write operations will not function.
SMSC LAN9217
83
Revision 1.8 (06-06-07)
DATASHEET
SMSC [ SMSC CORPORATION ]
