16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
BITS
DESCRIPTION
TYPE
DEFAULT
13-12
Threshold Control Bits (TR). These control the transmit threshold values
the MIL should use. These bits are used when the SF bit is reset. The host
can program the Transmit threshold by setting these bits. The intent is to
allow the MIL to transfer data to the final destination only after the threshold
value is met.
R/W
00
In 10Mbps mode (TTM = 1) the threshold is set as follows:
[13]
0
[12]
0
Threshold (DWORDS)
012h
018h
020h
028h
0
1
1
0
1
1
In 100Mbps mode (TTM = 0) the threshold is set by as follows:
[13]
0
[12]
0
Threshold (DWORDS)
020h
040h
080h
100h
0
1
1
0
1
1
11-7
6-5
Reserved
RO
-
PHY Clock Select (PHY_CLK_SEL). This field is used to switch between
the internal and external MII clocks (RX_CLK and TX_CLK). This field is
encoded as follows:
R/W
00b
[6] [5]
MII Clock Source
---------------------------------------------------
0
0
1
1
0
1
0
1
Internal PHY
External MII Port
Clocks Disabled
Internal PHY
Notes:
This field does not control multiplexing of the SMI port or other MII signals.
There are restrictions on the use of this field. Please refer to Section 3.11,
"MII Interface - External MII Switching," on page 41 for details.
4
Serial Management Interface Select (SMI_SEL). This bit is used to switch
the SMI port (MDIO and MDC) between the internal PHY and the external
MII port. When this bit is cleared to ‘0’, the internal PHY is selected, and all
SMI transactions will be to the internal PHY. When this bit is set to ‘1’, the
external MII port is selected, and all SMI transactions will be to the external
PHY. This bit functions independent of EXT_PHY_EN. When this bit is set,
the internal MDIO and MDC signals are driven low. When this bit is cleared,
the external MIDIO signal is tri-stated, and the MDC signal is driven low.
R/W
0
Note:
This bit does not control the multiplexing of other MII signals.
Revision 1.8 (06-06-07)
82
SMSC LAN9217
DATASHEET
SMSC [ SMSC CORPORATION ]
