16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
5.5.9
Special Modes
Index (In Decimal):
18
Size:
16-bits
ADDRESS
DESCRIPTION
TYPE
DEFAULT
15-8
Reserved
RW,
NASR
7:5
4:0
MODE: PHY Mode of operation. Refer to Table 5.9 for more details.
RW,
NASR
See
Table 5.9
PHYAD: PHY Address:
The PHY Address is used for the SMI address.
RW,
NASR
00001b
Table 5.9 MODE Control
DEFAULT REGISTER BIT VALUES
MODE
MODE DEFINITIONS
REGISTER 0
[13,12,10,8]
REGISTER 4
[8,7,6,5]
000
001
010
10Base-T Half Duplex. Auto-negotiation disabled.
10Base-T Full Duplex. Auto-negotiation disabled.
0000
0001
1000
N/A
N/A
N/A
100Base-TX Half Duplex. Auto-negotiation disabled.
CRS is active during Transmit & Receive.
011
100
100Base-TX Full Duplex. Auto-negotiation disabled.
CRS is active during Receive.
1001
1100
N/A
100ase-TX Half Duplex is advertised. Auto-
negotiation enabled.
CRS is active during Transmit & Receive.
0100
101
Repeater mode. Auto-negotiation enabled.
100Base-TX Half Duplex is advertised.
CRS is active during Receive.
1100
N/A
0100
110
111
Reserved - Do not set the LAN9217 in this mode.
All capable. Auto-negotiation enabled.
N/A
X10X
1111
Note 5.4
Note 5.4 When MODE=111, the register 0 bits 13 and 8 are variable dependant on the auto-
negotiated speed and duplex.
SMSC LAN9217
115
Revision 1.8 (06-06-07)
DATASHEET
SMSC [ SMSC CORPORATION ]
