16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
5.3.5
BYTE_TEST—Byte Order Test Register
Offset:
64h
Size:
32 bits
This register can be used to determine the byte ordering of the current configuration
BITS
DESCRIPTION
TYPE
DEFAULT
31:0
Byte Test
RO
87654321h
5.3.6
FIFO_INT—FIFO Level Interrupts
Offset:
68h
Size:
32 bits
This register configures the limits where the FIFO Controllers will generate system interrupts.
BITS
DESCRIPTION
TYPE
DEFAULT
31-24
TX Data Available Level. The value in this field sets the level, in number
of 64 Byte blocks, at which the TX FIFO Available interrupt (TFDA) will be
generated. When the TX data FIFO free space is greater than this value a
TX FIFO Available interrupt (TDFA) will be generated.
R/W
48h
23-16
15-8
7-0
TX Status Level. The value in this field sets the level, in number of
DWORDs, at which the TX Status FIFO Level interrupt (TSFL) will be
generated. When the TX Status FIFO used space is greater than this value
an TX Status FIFO Level interrupt (TSFL) will be generated.
R/W
R/W
R/W
00h
00h
00h
RX Space Available Level. The value in this field sets the level, in number
of 64 Byte blocks, at which the RX data FIFO Level interrupt (RDFL) will be
generated. When the RX data FIFO free space is less than this value an RX
data FIFO Level interrupt (RDFL) will be generated.
RX Status Level. The value in this field sets the level, in number of
DWORDs, at which the RX Status FIFO Level interrupt (RSFL) will be
generated. When the RX Status FIFO used space is greater than this value
an RX Status FIFO Level interrupt (RSFL) will be generated.
SMSC LAN9217
Revision 1.5 (07-18-06)
DATA7S7HEET
SMSC [ SMSC CORPORATION ]
