16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
5.3.4
INT_EN—Interrupt Enable Register
Offset:
5Ch
Size:
32 bits
This register contains the interrupt masks for IRQ. Writing 1 to any of the bits enables the
corresponding interrupt as a source for IRQ. Bits in the INT_STS register will still reflect the status of
the interrupt source regardless of whether the source is enabled as an interrupt in this register.
BITS
DESCRIPTION
Software Interrupt (SW_INT_EN)
TYPE
DEFAULT
31
30:26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
R/W
RO
0
-
Reserved
TX Stopped Interrupt Enable (TXSTOP_INT_EN)
RX Stopped Interrupt Enable (RXSTOP_INT_EN)
RX Dropped Frame Counter Halfway Interrupt Enable (RXDFH_INT_EN).
Reserved
R/W
R/W
R/W
RO
0
0
0
0
0
0
0
0
0
0
0
0
0
-
TX IOC Interrupt Enable (TIOC_INT_EN)
RX DMA Interrupt (RXD_INT).
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
GP Timer (GPT_INT_EN)
PHY (PHY_INT_EN)
Power Management Event Interrupt Enable (PME_INT_EN)
TX Status FIFO Overflow (TXSO_EN)
Receive Watchdog Time-out Interrupt (RWT_INT_EN)
Receiver Error Interrupt (RXE_INT_EN)
Transmitter Error Interrupt (TXE_INT_EN)
Reserved
TX Data FIFO Underrun Interrupt (TDFU_INT_EN)
TX Data FIFO Overrun Interrupt (TDFO_INT_EN)
TX Data FIFO Available Interrupt (TDFA_INT_EN)
TX Status FIFO Full Interrupt (TSFF_INT_EN)
TX Status FIFO Level Interrupt (TSFL_INT_EN)
RX Dropped Frame Interrupt Enable (RXDF_INT_EN)
RX Data FIFO Level Interrupt (RDFL_INT_EN)
RX Status FIFO Full Interrupt (RSFF_INT_EN)
RX Status FIFO Level Interrupt (RSFL_INT_EN)
GPIO [2:0] (GPIOx_INT_EN).
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
000
8
7
6
5
4
3
2-0
Revision 1.5 (07-18-06)
SMSC LAN9217
DATA7S6HEET
SMSC [ SMSC CORPORATION ]
