16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
5.3
System Control and Status Registers
Table 5.1, "Direct Address Register Map", lists the registers that are directly addressable by the host
bus.
Table 5.1 Direct Address Register Map
CONTROL AND STATUS REGISTERS
BASE ADDRESS
+ OFFSET
SYMBOL
REGISTER NAME
Chip ID and Revision.
DEFAULT
50h
54h
58h
5Ch
60h
64h
68h
6Ch
70h
74h
78h
7Ch
80h
84h
88h
8Ch
90h
94h
98h
9Ch
A0h
A4h
ID_REV
IRQ_CFG
See Page 72.
00000000h
00000000h
00000000h
-
Main Interrupt Configuration
Interrupt Status
INT_STS
INT_EN
Interrupt Enable Register
Reserved for future use
Read-only byte order testing register
FIFO Level Interrupts
RESERVED
BYTE_TEST
FIFO_INT
87654321h
48000000h
00000000h
00000000h
00000800h
00000000h
00000000h
00001200h
00000000h
00000000h
0000FFFFh
0000FFFFh
-
RX_CFG
Receive Configuration
TX_CFG
Transmit Configuration
HW_CFG
Hardware Configuration
RX Datapath Control
RX_DP_CTL
RX_FIFO_INF
TX_FIFO_INF
PMT_CTRL
GPIO_CFG
GPT_CFG
GPT_CNT
Receive FIFO Information
Transmit FIFO Information
Power Management Control
General Purpose IO Configuration
General Purpose Timer Configuration
General Purpose Timer Count
Reserved for future use
WORD SWAP Register
RESERVED
WORD-SWAP
FREE_RUN
RX_DROP
MAC_CSR_CMD
00000000h
-
Free Run Counter
RX Dropped Frames Counter
00000000h
00000000h
MAC CSR Synchronizer Command (MAC
CSR’s are indexed through this register)
A8h
ACh
MAC_CSR_DATA
AFC_CFG
MAC CSR Synchronizer Data
Automatic Flow Control Configuration
EEPROM Command
00000000h
00000000h
00000000h
00000000h
-
B0h
E2P_CMD
B4h
E2P_DATA
EEPROM Data
B8h - FCh
RESERVED
Reserved for future use
SMSC LAN9217
Revision 1.5 (07-18-06)
DATA7S1HEET
SMSC [ SMSC CORPORATION ]
